soloktanjung
Full Member level 6
Hello friends,
I am compiling a VHDL testbench below and got the following modelsim error:
I tried many things such as declare a signal using time type but still unable to fix it.
Can anyone give suggestions on how to fix this error or how the other ?
Thanks in advance.
Hairo
I am compiling a VHDL testbench below and got the following modelsim error:
Code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
signal TDI_TMS : bit_vector(1 downto 0);
for m in 0 to 14 loop
TDI_TMS <= ('1', '0') after (1201 + 3000*m); -- line 170
end loop
Code:
# ** Error: tb_top1.vhd(170): Type error resolving infix expression "+" as type std.standard.time.
I tried many things such as declare a signal using time type but still unable to fix it.
Can anyone give suggestions on how to fix this error or how the other ?
Thanks in advance.
Hairo