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simple verilog doubt by verilog beginner

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srinpraveen

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I have a logic that happens at every rising clock edge. I want to do a simple action. I will tell you the situation.

signal a should be 0 as long as signal b is 1. How do i implement this in verilog code other than the conventional if else happening at always @(posedge clk or negedge rst_n) to check this ??

Is there some verilog construct (I mean synthesizable verilog construct) like signal a=0 until signal b=1 ??
 

I'm not sure I understood, but a NOT gate could be for you!
 

Well, I will think I have not worded my question properly. I will think of a way to re-word my question. I will be back to this thread in a couple of days.
 

a <= not b, where a and b are youre 2 signlas it's jus an assigment(the sintax i used is in vhdl however it is simple to find the verilog analogy) Hope this helped...
 

Yes it did. Thanks buddy. (just a bit new to verilog buddy...so making some silly mistakes in the thought process:grin:)
 

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