analog DLL stability issues

I'm designing an analog DLL which
consists of PHD , Charge Pump, and
Delay chain. Actually it is very similar
to a PLL except Delay chain replacing
VCO. Does this kind of DLL have stability
concern? And How can I check it's Phase
Margin?

Thanks!

dll.stabilität download

is there any reason you went with a delay chain instead of a ring oscillator? This DLL will have almost the same set of stability issues associated with PLLs, plus I dont see how you can gain anything using the delay chain instead of the vco. Basically, you are paying the price of a pll but getting performance of a DLL...

Can you please post about the application for your design?

dll stability

My DLL can provide variable output delays
like 20% 25% 33% and so on with different delay stages. But VCO can't. As you said, this DLL has
same stability concern with PLL. Can I check stability
of DLL in the same way as PLL? But for DLL, what's
the gain for delay chain , the counterpart of VCO gain,?

dll stablity

There is a difference w.r.t. stabiltiy.
A PLL will at least have one pole (ideal integrator) from the VCO (voltage to frequency conversion, so you have to integrate to get the phase transfer -> VCO transfer = Kvco/p with Kvco in rad/V*s).
To get zero phase difference you'll have to create one extra integrator in the loop, so you end up with a second order system, which can get instable if you don't introduce a zero.

The DLL does not have the pole from the VCO: the delay line is a voltage to phase conversion (delay line gain rad/V)
So when introducing one integrator in the loop to get zero phase difference, you'll end up with a first order system which is unconditionally stable.
Still you have to watch out for parasitic poles, introduced inside your loop, so you might end up with a second order system.

p.s. a DLL can give better noise performance at low frequency offsets w.r.t. a PLL, because the regenerative nature of the VCO will increase the noise near the carrier. A DLL will be "reset" by the reference on each input edge.

Sceptre

DLL stability

I think this kind of DLL have no stability
concern! Its phase margine is 90.

DLL stability

I agree, but simple current-starved inverter delay line will make the phase noise of the input clk to be worse, isn't it?

Re: DLL stability

CML style delay cell with regulated supply will reduce injection of supply noise .It will certainly help if you are designing high speed DLL

Re: DLL stability

I AM ALSO WORKING ON THE SAME THING WILL YOU TELL ME WHAT YOU HAVE DONE AND FURTHER WHAT CAN BE DONE.I HAVE STUIDED PLL AND DLL BLOCK DIAGRAM FROM WHERE I SHOULD START DESIGNING PORTION ON PAPER.PLEASE HELP