questasim post fit simulation input signals ont visible in waveform window

Problems with Integrating Xilinx 9.1 ISE with Questasim 6.4c

I wrote a Verilog code for clock divider and also its test bench in Xilinx 9.1 ISE.

I had integrated Questasim 6.4c with Xilinx 9.1 ISE and using Modelsim SE Verilog for Simulation.

After compiling the code, it showed no errors.
Hence, I went ahead with behavioral simulation....I got the following message in questasim's command window
# Reading C:/questasim_6.4c/tcl/vsim/pref.tcl
# // QuestaSim 6.4c Dec 8 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do {sysclkdivider_tb.fdo}
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim vlog 6.4c Compiler 2008.12 Dec 8 2008
# -- Compiling module sysclkdivider
#
# Top level modules:
# sysclkdivider
# QuestaSim vlog 6.4c Compiler 2008.12 Dec 8 2008
# -- Compiling module sysclkdivider_tb
#
# Top level modules:
# sysclkdivider_tb
# QuestaSim vlog 6.4c Compiler 2008.12 Dec 8 2008
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L cpld_ver -L uni9000_ver -lib work -t 1ps sysclkdivider_tb glbl
# Loading work.sysclkdivider_tb(fast)
# Loading work.glbl(fast)
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# ** Error: (vish-4014) No objects found matching '*'.
# Error in macro ./sysclkdivider_tb.fdo line 10
# (vish-4014) No objects found matching '*'.
# while executing
# "add wave *"

Later I went to Work-> Right clicked on sysclkdivider(my module name) -> Simulate

Then, I could see all the objects in my design in the objects window. I added them to waveform window and could run it. i could see the waveforms in the questasim's waveform window and found them correct.

Is this procedure correct? I think it should directly simulate when I click on Simulate Behavioral Model in Xilinx ISE.


When I chose Post-fit Simulation in Xilinx ISE, and clicked on Simulate Post-fit model under Processes tab, it carried out synthesis..fit..etc., and all the processes were successful. Then, immediately questasim got opened..with the following message in the command window:

# Reading C:/questasim_6.4c/tcl/vsim/pref.tcl
# // QuestaSim 6.4c Dec 8 2008
# //
# // Copyright 1991-2008 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do {sysclkdivider_tb.tdo}
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim vlog 6.4c Compiler 2008.12 Dec 8 2008
# -- Compiling module sysclkdivider
# -- Compiling module glbl
#
# Top level modules:
# sysclkdivider
# glbl
# QuestaSim vlog 6.4c Compiler 2008.12 Dec 8 2008
# -- Compiling module sysclkdivider_tb
#
# Top level modules:
# sysclkdivider_tb
# QuestaSim vlog 6.4c Compiler 2008.12 Dec 8 2008
# -- Compiling module glbl
#
# Top level modules:
# glbl
# vsim -L simprims_ver -lib work -t 1ps +maxdelays sysclkdivider_tb glbl
# ** Note: (vsim-3812) Design is being optimized...
# Loading work.sysclkdivider_tb(fast)
# Loading simprims_ver.X_BUF(fast)
# Loading simprims_ver.X_INV(fast)
# Loading simprims_ver.X_XOR2(fast)
# Loading simprims_ver.X_OR2(fast)
# Loading simprims_ver.X_FF(fast)
# Loading simprims_ver.X_AND2(fast)
# Loading work.glbl(fast)
# Loading instances from netgen/fit/sysclkdivider_timesim.sdf
# Loading timing data from netgen/fit/sysclkdivider_timesim.sdf
# ** Note: (vsim-3587) SDF Backannotation Successfully Completed.
# Time: 0 ps Iteration: 0 Region: /sysclkdivider_tb File: sysclkdivider_tb.v
# .main_pane.mdi.interior.cs.vm.paneset.cli_0.wf.clip.cs.pw.wf
# ** Error: (vish-4014) No objects found matching '/glbl/PRLD'.
# Error in macro ./sysclkdivider_tb.tdo line 13
# (vish-4014) No objects found matching '/glbl/PRLD'.
# while executing
# "add wave /glbl/PRLD"


In the objects window, I could see only the output signals of my module. Hence when I run the simulation I am able to see only the output signal's waveforms and not input signals.

Is there a way so that I can see the input signals as well so that I can easily estimate the delay by comparing with behavioral simulation waveforms???

Please help.