+ Post New Thread
Results 1 to 3 of 3
  1. #1
    Full Member level 2
    Points: 1,895, Level: 10

    Join Date
    Jun 2007
    Posts
    122
    Helped
    0 / 0
    Points
    1,895
    Level
    10

    Interview Question: Verilog Code To Find Duration Of Clock

    Hi All,

    Can anybody help me answering a question.

    Note:- Don't as Jitter, Set-Up, Hold Time Values. I need Verilog logic.

    How can i find a duration of a given (Clock) using Verilog. There are two cases when

    1) Duty Cycle is 50%

    2) Duty Cycle is 30%

    Please help me it's important

    •   AltAdvertisment

        
       

  2. #2
    Advanced Member level 3
    Points: 4,234, Level: 15

    Join Date
    Aug 2010
    Location
    San Jose area
    Posts
    701
    Helped
    197 / 197
    Points
    4,234
    Level
    15

    Re: Interview Question: Verilog Code To Find Duration Of Clock

    If you try it and show some effort, we'll help you.



    •   AltAdvertisment

        
       

  3. #3
    Full Member level 3
    Points: 3,119, Level: 13
    Achievements:
    7 years registered

    Join Date
    May 2007
    Posts
    178
    Helped
    35 / 35
    Points
    3,119
    Level
    13

    Re: Interview Question: Verilog Code To Find Duration Of Clock

    It should look something like this:

    initial begin
    #500; // wait clock to be stable
    @(posedge clk) t1 = $time;
    @(posedge clk) t2 = $time;
    $write ("The period is : %t", t2-t1);
    end



--[[ ]]--