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But dummy transistor should be fed with inverted control signal,then how can I generate inverted signal as the bootstrap switch is controlled by some complex circuitary.....
@leo_o2:voltage between G and S is the control signal for main switch,I don't have any idea of how to invert it.Even if I use some inverting circuit then there will be delay between signals which deteriorate even more..
Hi all,
I've attached my DAC snapshot.Currently I'm simulating it with only one capacitor,I need to extend it 8 more capcitors.If I use same sample and hold circuits to drive all my capacitors,it couldn't follow input signal.Can I use seperate S/H for every capacitor(will there be any problems with sampling time skew)?
Parasitics at the top plate of capacitor are hugely effecting the voltage at that terminal, If I use higher capacitance then my circuit is becoming very much slow.This is my sample and hold circuit https://obrazki.elektroda.pl/96_1297770660.png
It seems,to me,that without using any analog buffers or Opamps I can achieve 500MHz sampling rate.The only problem is that I need to use seperate S&H circuit(a total of 27) for each capacitor.Will there be any problem because of skew and jitter in Sampling signal??
I haven't considered the effects of mismatch and PVT.What is extra circuitary(like Bandgap Reference or voltage reference) do I need to use??
mismatch might be the killer if u use seperate s/h and also more area. extra circuit such as bandgap will be needed to generate all ur common mode volatges and reference current.
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