Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Turning VHDL synthesizable code into VHDL emulator

Status
Not open for further replies.

omara007

Advanced Member level 4
Joined
Jan 6, 2003
Messages
1,237
Helped
50
Reputation
102
Reaction score
16
Trophy points
1,318
Location
Cairo/Egypt
Activity points
9,716
Is there any way to turn your VHDL synthesizable code into an emulator to the same system your VHDL describes ?
In other words .. let's say you are designing a microprocessor using VHDL ( or even verilog ) .. and now you are done with your design and simulation .. your simulation gave u correct output for your stimulus .. but you have a real program compiled to your designed microprocessor, how can you make use of your HDL to run that program on it , exactly as if it was a real microprocessor ..
simply converting ur code into emulator ..


Do you guys ahve any idea if this is feasible or not ?
 

vhdl emulation for fpga

One such approach can be found here:
 

emulator vhdl

Ok if i understand an EMULATOR is different from a SIMULATOR in the sens that the concept applies to CPUs and by abuse of language to memory and other pairs of similar devices .I used to work with a LASER EMULATORS .. the real thing was very expensive .So we used some LEDs ..But still DIODES as the LASER . In the case of the CPU means that in an EMULATOR you run the CODE in real CONDITIONS and in a simulation you run the program code in VIRTUAL condition .. Now to apply such a concept to a HARDWARE language DESCRIPTION this a little more involving because you deal with just HARWARE . this is yes describedd by software means ,but the final object is HARWARE not two instances .So in that regard you can't emulate it ..you can simulate it ... Well all this because of semantics !.. In the case of a EPROM emulator the replacement architecture is very close of the EPROM as well as in the LASER diodes . in the case of a HDL description .. The harware once again is not genaraly there avalaible in a similar form ! . SO how can you EMULATE it?? Any form of REPLACEMENT HARDWARE that is NOT close enough of the HDL desription wouldn't be an EMULATION .. but an ACCELERATED SIMULATION !
 

processor designing using vhdl

elton ..
fogive me for not being very able to get all what u said :)
but anyhow .. let me clarify more ..
do u know Seamless CVE ? ... do u know ARMulator ? .. i mean something like ARMulator .. but for a processor I designed .. not a readilu available processor design written in C for example ..
got me ?
 

designing processor using vhdl

geconom

the link u sent is somehow midway to my target .. they design using HDL .. and test with a real program compiled using Keil .. yet, everything is still considered simulation .. not emulation ..

I'll give an example to make u feel what i want ..

can u design an intel microprocessor using VHDL .. and when ur done , u run windows over this VHDL code ? .. this is considered emulating the processor ..
this is already available in some tools .. like Seamless tools .. and all available processor emulators .. but i guess most of these emulators are already done as software program .. what i'm willing to find is a tool that u put ur VHDL code on .. and it will convert the synthesizable code into an emulator to what this code represents .. and hence u can emulate ur code regardless of being bug free or buggy ..

that will help too much testing ur design in a better way ..
 

vhdl software emulation

I worked with Seamless last year so I understand what you mean. I remember that it is based on processor support modules (PSPs) which include an instruction set simulator (ISS) and all required interfaces to connect the ISS with a VHDL I/O description of the processor, Denali memory manager for external memories and a special module, which if I am not wrong was a memory mapped text screen. The processor description in VHDL is not needed under this approach.

For thing to work the way you say, I assume you need a tool to automatically generate an ISS (+ any required interfaces with other modules) from a VHDL processor description. I am not aware of such a tool but since these tools are part of a larger environment, I suggest to check with Mentor if they have or plan to release such a tool.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top