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Second clock input in Xilinx FPGA question.

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kostbill

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Hello.

I am having weird problems with my design and I suspect that perhaps it is a timing error. I don't know what else to assume.

I am using microblaze. I want to connect a peripheral with the PLB bus.

So, in my design, I have an asynchronous block, communicating with an external peripheral, the external peripheral provides the clock. The input in the FPGA is from a CLKIN pin.

My question is, if I am declaring this correct in the UCF file.


Net fpga_0_my_i2s_0_BCLK_pin TNM_NET = E10;
TIMESPEC TS_fpga_0_my_i2s_0_BCLK_pin = PERIOD fpga_0_my_i2s_0_BCLK_pin 4000 kHz;
Net fpga_0_my_i2s_0_BCLK_pin LOC=E10 | IOSTANDARD = LVCMOS33;

If it is not correct, can you suggest something else? Does it need anything else? Is it just this?

Thanks,
Bill.
 

Bill,

Your UCF syntax looks OK.

If I understand what you describe, you have the uBlaze running on one clock, and your PLB device running on a different clock. This can cause problems.

Look carefully at the TWR file, and see what signals start on one clock and end on another. All of these signals will need logic to handle the clock crossing.

Hope that helps,
RK
 

Hi!

I solved that problem by doing the second clock a plain input. Then the main PLB clock checks the rising edge of my other clock with a small synchronization process.

Thanks.
 

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