user_asic
Advanced Member level 4
I need a way to test all clbs in a virtex 4 and virtex 5 fpga. But I can't seem to find any sample designs that show how to do this. Most research papers focus on BIST techniques, which is beyond my skill level without any sample designs to look at.
Can anyone point me to some sample designs (no ambiguous tutorials please, as I've probably seen them all), offer any tips, or give a overview of how it is done.
Thanks
Can anyone point me to some sample designs (no ambiguous tutorials please, as I've probably seen them all), offer any tips, or give a overview of how it is done.
Thanks