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The details is that i fellow copy the directory from /tools/cds5/tools.lnx86/dfII/sample/tutorial/le/cell_design to my home (root account) directory, then use the "basic" library cell view of "nand2' & "Inv" i create a 2-input XOR.
After extracted view is generated, use it to compare with schematic of 2-input XOR and run LVS, that dispalying this message:
Analysis Job Failed
! job '/root/cell_design/LVS' that was started at 'May 1700:08:28 2004' has failed.
Press OUTPUT button, that shown
Can't find/read file '/root /cell_design/LVS/si.out'.
View the LVS.log that shown
Running simulation in directory: "/root/cell_design/LVS".
Begin netlist: May 17 00:08:39 2004
view name list = ("auLvs" "extracted" "schematic")
stop name list = ("auLvs")
library name = "project"
cell name = "XOR2"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance +41 in cellView (XOR2 extracted) from viewlist 'auLvs extracted schematic ' in library 'project'.
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance +40 in cellView (XOR2 extracted) from viewlist 'auLvs extracted schematic ' in library 'project'.
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance +39 in cellView (XOR2 extracted) from viewlist 'auLvs extracted schematic ' in library 'project'.
...
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