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Error in Assura DRC: BAD_SUBSTR_SUBTAP_MULTCONN_ERC

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thevan48

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hi everybody,
I'm using hitkit 3.72 AMS for techno H35B4, when i check Assura-DRC this error message appears: BAD_SUBSTR_SUBTAP_MULTCONN_ERC.
Can you help me plz!
Thanks
 

error in Assura DRC

Check this error message string in your Assura DRC (or ERC) rules' file. The rule violation generating this error message should give you a hint. I'd suspect that your substrate taps are connected to different nodes, which is not allowed.
 

Re: error in Assura DRC

erikl said:
Check this error message string in your Assura DRC (or ERC) rules' file. The rule violation generating this error message should give you a hint. I'd suspect that your substrate taps are connected to different nodes, which is not allowed.
Click to expand...

I have 3 legs CMOS connected in series for amplification, it notifies "Bad_substrate_subtap_multiconn" in 3 PMOS. As i understand, i have to connect substrate tap of 3 PMOS with Vdd, right?
Tks for replying
 

Re: error in Assura DRC

thevan48 said:
As i understand, i have to connect substrate tap of 3 PMOS with Vdd, right?
Click to expand...
Not necessarily: Yes, if all of them are in the same n-well. If you use 4-terminal PMOSFETs, you may, however, grant each PMOS its own n-well. In this case you may connect each n-well tap to the source of its PMOS. The n-wells not connected to Vdd are called hot n-wells and need more spacing, s. DRC rules.
 

Re: error in Assura DRC

erikl said:
thevan48 said:
As i understand, i have to connect substrate tap of 3 PMOS with Vdd, right?
Click to expand...
Not necessarily: Yes, if all of them are in the same n-well. If you use 4-terminal PMOSFETs, you may, however, grant each PMOS its own n-well. In this case you may connect each n-well tap to the source of its PMOS. The n-wells not connected to Vdd are called hot n-wells and need more spacing, s. DRC rules.
Click to expand...

I tried to connect the n-well to Vdd by different layers (ntap, ndiff) but there's always this error. I show my layout, which layer should i connect by?
Thanks
 

Re: error in Assura DRC

thevan48 said:
I tried to connect the n-well to Vdd by different layers (ntap, ndiff) but there's always this error. I show my layout, which layer should i connect by?
Click to expand...
N-well taps (as well as substrate taps) must always be connected to their respective potential by metal layer(s), usually by contact to M1!
 

error in Assura DRC

As your error state "BAD_SUBSTR_SUBTAP_MULTCONN_ERC" could mean your substrate tap need connect together by metal1
 

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