calibre LVS empty cells

hi
i'm in an ASIC design project .
synthesis is done by synopsys design compiler .
placement and routing by first encounter.
we use standard cells of tsmc 90nm
calibre is used for verification (DRC/LVS/PEX)

when i try to run LVS : it flags this error
error:no module for cell <cell_name> ( it flags the same error for all cells)

WARNING: Cell CLKINVX1 is referenced but not defined. Empty cell used.

then the run is aborted with error =" can not read source"

..........................................
my question :
how to correct this?
what are exactly the required tech. files ( other than the golden_rules svrf file?) .. how to add the lef files used and .db files used in the syntehsis and layout (first encounter layout generation) to calibre ?


thx

hello

while doing LVS. it is needed to specify the spice files of all the tsmc 90 tech tht used in the design along with the spice file of the design itself.


S

You need add the spice library in your source list. If you dont add, then calibre may not know the cell functionality & LVS wont be perfect.