I am currently designing a Serdes chip including the multiplexer, PLL; demultiplexer, CDR. But I am not sure about how to determine the component parameters according to the BER requirement. Here is my idea:

First, the Serdes needs satisfy the BER requirement, for example, smaller than 10^(-12). Then, through the erfc function, we can get the SNR requirement, the signal power relates to the output swing, the noise power relates to many factors, for example, the CDR and the demux noise. And of course, there are other requirements such as the jitter tolerance, jitter transfer and jitter generation need to be satisfied.

So, is that correct that I first determine the total noise, and then based on the jitter mask requirements, I tune the component parameters and the output swing to satisfy the noise requirements so that the BER is met?

Also, I found some references in which the BER is related with the peak-peak jitter and the RMS jitter. In that way, it seems the jitter histogram curve is needed through the simulation. But the simulation result is also determined by the simulation times I chose.

Could anyone who has the experience give me suggestions about the steps to determine the component values according to the BER requirement in a serdes design?

Thanks a lot!