kuntul
Newbie level 6
I have a verilog code below.
The problem is that the output, which is ForwardA and ForwardB is not updated not on the rising clock edge rather than on the next rising clock edge... why is this?? How do I resolve so that the output is updated on the same positive rising clock edge?
Here's an image to clarify my point:
**broken link removed**
ForwardA is updated with 2 on the next rising clock edge and not on the same rising clock edge. How do I make it so that it updates on the first rising clock edge as it already satisfies the if statement there.
Code:
always @(posedge Clk) begin
ForwardA = 0;
ForwardB = 0;
//EX Hazard
if (EXMEMRegWrite == 1) begin
if (EXMEMrd != 0)
if (EXMEMrd == IDEXrs)
ForwardA = 2'b10;
if (EXMEMrd == IDEXrt && IDEXTest == 0)
ForwardB = 2'b10;
end
//MEM Hazard
if (MEMWBRegWrite == 1) begin
if (MEMWBrd != 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrs)))
if (MEMWBrd == IDEXrs)
ForwardA = 2'b01;
if (IDEXTest == 0) begin
if (!(EXMEMRegWrite == 1 && EXMEMrd != 0 && (EXMEMrd == IDEXrt)))
if (MEMWBrd == IDEXrt)
ForwardB = 2'b01;
end
end
end
endThe problem is that the output, which is ForwardA and ForwardB is not updated not on the rising clock edge rather than on the next rising clock edge... why is this?? How do I resolve so that the output is updated on the same positive rising clock edge?
Here's an image to clarify my point:
**broken link removed**
ForwardA is updated with 2 on the next rising clock edge and not on the same rising clock edge. How do I make it so that it updates on the first rising clock edge as it already satisfies the if statement there.
