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[help] on-chip crystal oscillator design

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one-pin crystal oscillator

i'm a digital designer, but now i'm designing a on-chip crystal oscillator with freq is 48M, can any one give me some artical or papers on desing the oscillator?
or can only one give me a 48M quartz hspice simulator model?
thans!![/b]
 

pspice quartz oscillator sim

1. use need 48M Xtal spice R-L-C model ..
2. use AC sim check invert + Xtal have 180 degree phase shift
and frequency = Xtal freq
3. check invert gain
4. close loop use .tran and you must be use hspice .option
method=gear or trap ..
5. assign a initial voltage let spice sim speed up
6. make sure Xtal can really osc

ps. sometime hspice sim Xtal is work but real ASIC is not ..
you should becareful use .option parameter
 

First AC analysis to check your loop gain is >1 when phase shift is 180 degree. Use linear frequency scale with very narrow range close to expected frequency.
Put all component in your simulation circuit including device pin capacitance (PAD to substrate) and possible PCB stray capacitance.
Better to take figure of merit for loop gain more than 2.
When you will verify oscillator by transient analysis use conservative simulator options.
Quartz oscillator has long start up time so your simulation time should be more than Q*T, where Q is quality factor in your RLC model, T is time period of oscillation.
 

Hi,
I guess you will be using some sort of invertor inside the chip. Be aware of
1) Specified load capacitance. Take into consideration the pin and the parasitic capacitance.
2) Start up problems.
Hope this helps,
BRMadhukar
 

andy2000a said:
1. use need 48M Xtal spice R-L-C model ..
2. use AC sim check invert + Xtal have 180 degree phase shift
and frequency = Xtal freq
3. check invert gain


but the inv+Xtal is close loop system,how to simulate openloop gain?
can you post your spice command config?
Click to expand...
 

who has the sim file of crystal oscillators? could you post it ?
 

There are some books on crystal oscillators in the e-book forum
 

increase the openloop gain when 0 phase shift
set the initial current of L in crystal model to speed up the tran simulation.
 

Jet_wu said:
increase the openloop gain when 0 phase shift
set the initial current of L in crystal model to speed up the tran simulation.
Click to expand...
I don't understand what you said, could you modify my sim file to make it work? tks a lot!

MY SIM FILE:
vdd vdd gnd pwl(0u 0v 5000u 3v)
.option post=2
.tran 1u 200000u
.lib 'MYLIB.lib' tt

MP2 OSC2 OSC1 VDD VDD PCH L=2U W=400U
MN2 OSC2 OSC1 0 0 NCH L=2U W=200U

RF OSC1 OSC2 15000K

R1 OSC1 N1N13 30K
C1 N1N13 N1N55 0.003P
L1 N1N55 OSC2 7863H
CO OSC1 OSC2 1.5P

CL2 OSC2 0 8P
CL1 OSC1 0 8P
.END
 
Last edited by a moderator:

Here is my verified crystal model .
Adjust the init current to speed up the oscillation start-up time .
.subckt QZS12MHz 1 2
*
lqz 1 11 0.1H IC=1e-07
cs 11 12 1.75fF
rqz 12 2 40
cp 1 2 5pF
.ends
 

you'd better change the timestep to 0.5n and reduce the rise time of vdd. There is no need to run so much time.
add ".opt accurate"
 

Nobody said:
Here is my verified crystal model .
Adjust the init current to speed up the oscillation start-up time .
.subckt QZS12MHz 1 2
*
lqz 1 11 0.1H IC=1e-07
cs 11 12 1.75fF
rqz 12 2 40
cp 1 2 5pF
.ends
Click to expand...
thank you very much, i'll try.
but do you mean if there has enough sim time, the ic value is not need?
 

Jet_wu said:
you'd better change the timestep to 0.5n and reduce the rise time of vdd. There is no need to run so much time.
add ".opt accurate"
Click to expand...
tks a lot, i'll try.
 

The xtal's Q is very high ( 10^4 ~ 10^5) .
The LRC envelop transition time constant is propotional to its Q(quality factor) . So it take very long time to achive the full swing . Due to its high Q , the equivalent impedance is quite high and that get very small feedback . The oscillation depend strongly on this small feedback voltage as well as correct phase. It's easy to lose oscillation once your simulator roundoff or other numerical accuracy's problem . This sounds like communication or ADC's S/N ratio. The signal part dominate from IC setting . The noise come from the computer/simulator accuracy. The oscillation condition will be lost with lower S/N ratio .
 

Jet_wu said:
you'd better change the timestep to 0.5n and reduce the rise time of vdd. There is no need to run so much time.
add ".opt accurate"
Click to expand...
Jet_wu, tk u very much.
my circuit works well now, the most impotant thing is add ".opt accurate".
tks again!
 

Nobody said:
The xtal's Q is very high ( 10^4 ~ 10^5) .
The LRC envelop transition time constant is propotional to its Q(quality factor) . So it take very long time to achive the full swing . Due to its high Q , the equivalent impedance is quite high and that get very small feedback . The oscillation depend strongly on this small feedback voltage as well as correct phase. It's easy to lose oscillation once your simulator roundoff or other numerical accuracy's problem . This sounds like communication or ADC's S/N ratio. The signal part dominate from IC setting . The noise come from the computer/simulator accuracy. The oscillation condition will be lost with lower S/N ratio .
Click to expand...

I through you opinion is right, tks a lot.
 

ysz said:
Nobody said:
Here is my verified crystal model .
Adjust the init current to speed up the oscillation start-up time .
.subckt QZS12MHz 1 2
*
lqz 1 11 0.1H IC=1e-07
cs 11 12 1.75fF
rqz 12 2 40
cp 1 2 5pF
.ends
Click to expand...
thank you very much, i'll try.
but do you mean if there has enough sim time, the ic value is not need?
Click to expand...
My problem was the circuit didn't work, add ic value just speed up the oscillate time.
 

Humungus said:
There are some books on crystal oscillators in the e-book forum
Click to expand...

Could you poost e-book wed for me reference?
 

Could you teaches me how to do crystal OSC tran analysis.

Hi ysz
Your circuit, is right?

thx.
 

I am a new comer, who can give your theory induce process about CMOS crystal osc and design notice or paper, thanks!
 

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