Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Cadence, shortened net, global pins

Status
Not open for further replies.

streamc

Junior Member level 2
Joined
May 13, 2009
Messages
20
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,411
1) When I try to short pins such as vdda! with pin created by me I see errors.
2) Also When I try to short pins vdda with vdde I see errors.What the problem?
3) How create global pins in schematic without making that on symbol? I need to use pins with same names in upper scheme of ierarchy.

**broken link removed**
**broken link removed**

How can I solve these problems?

4) How can I create pin that will be used in Schematic scheme and in the upper ierarchy of Schematic scheme?

I need to short vdda or vdde with pins because i shortened them with a bulk of pmos4 everywhere in schemes of project,
Different signal to different pmos4.
I need to add signal such as power to vdda thar i short with bulk.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top