Elyments
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Hi,
For a VLSI project I was tasked to design a CMOS sixth order low pass filter in a 0.8u process, i created one using the standard VCVS 2nd order design with matching R and C values to create Butterworth characteristics and then cascading three stages with appropriate gains to make a 6th order filter.
My problem is that i have no idea how to make an estimate of my filters power consumption! I would really appreciate any advice on where to start! I've attached a multisim design of my filter, ive also created it in tanner tools L-Edit.
Thanks in advance,
Elyments
For a VLSI project I was tasked to design a CMOS sixth order low pass filter in a 0.8u process, i created one using the standard VCVS 2nd order design with matching R and C values to create Butterworth characteristics and then cascading three stages with appropriate gains to make a 6th order filter.
My problem is that i have no idea how to make an estimate of my filters power consumption! I would really appreciate any advice on where to start! I've attached a multisim design of my filter, ive also created it in tanner tools L-Edit.
Thanks in advance,
Elyments