Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

question in postlayout simulation

Status
Not open for further replies.
M

malolo

Junior Member level 1
Joined
Feb 25, 2009
Messages
17
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,381
Hi all,
I tried post-layout simulation for a simple inverter, in the spectre.out file, it says:

Notice from spectre during topology check.
Only one connection to node 'vdd!'

and output waveform confirmed that vdd is not actually supplied to internal transistors of the symbolized, extracted inverter. The vdd pin in the inverter is set to inputout(I/O type), connected(status) as shown below?

so what should i do to have the vdd supply really affect the inverter?
thanks a lot,
Kevin


[/img]
 

I can't see any metal wire connections in your extracted view. Did you run LVS successfully?
 

LVS run is successful, cell with extracted capacitors is shown below.




 

malolo said:
LVS run is successful, cell with extracted capacitors is shown below.
Click to expand...
I really can't find a reason, sorry! Check your Spectre netlist if it really contains the global vdd! and vss! nodes where necessary. If not, supply the missing "!" manually and re-simulate (without another netlisting, of course).
And may be the short-cut between gnd! and the "0" node is missing?
Good luck! erikl
 

thanks anyway Erikl, i'll keep looking
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top