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    ESL and Verification

    Hi,
    Does any one have idea about how ESL effects current functional verification methods (vmm,ovm etc)
    thank you

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    Re: ESL and Verification

    ESL is a catch all for different tools and languages. you need to be more specific with your question.
    regards
    ajay
    http://edaindia.com/wiki/esl


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    Re: ESL and Verification

    ESL is a way to provide you to translate the C model to RTL code!



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    Re: ESL and Verification

    Quote Originally Posted by ajayj
    ESL is a catch all for different tools and languages. you need to be more specific with your question.
    regards
    ajay
    http://edaindia.com/wiki/esl
    Hi thank you for your reply
    my question is
    if
    1.ESL to RTL(using some tool) is possible
    2.formal verification between esl and rtl is also possible..
    then functional verification will happen at ESL level by the designer(not at RTL level).
    That means.. there will not be the need of vmm/ovm etc. is that a bad sign for verification in future?
    Please correct me if I am wrong...



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    Re: ESL and Verification

    C to RTL convertion is possible but the code which u get will never be optimized.
    The re is a tool called catapultC which does this. The RTL works file but the u can not meet the design requirements. Even the RTL it generates will not be in readable format. So you cant work on it.
    So OVM or other verification methods are here to stay.



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    Re: ESL and Verification

    Quote Originally Posted by rama_bing
    Quote Originally Posted by ajayj
    ESL is a catch all for different tools and languages. you need to be more specific with your question.
    regards
    ajay
    http://edaindia.com/wiki/esl
    Hi thank you for your reply
    my question is
    if
    1.ESL to RTL(using some tool) is possible
    2.formal verification between esl and rtl is also possible..
    then functional verification will happen at ESL level by the designer(not at RTL level).
    That means.. there will not be the need of vmm/ovm etc. is that a bad sign for verification in future?
    Please correct me if I am wrong...
    VMM/OVM both are moving to embrace ESL - via TLM connections to SystemC etc. See updates on the respective sites. BTW - ESL synthesis is still maturing and it is unlikely to take away RTL for atleast 5 years, so jobs are more and more on VMM/OVM for now..

    Ajeetha, CVC
    www.cvcblr.com



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    Re: ESL and Verification

    Quote Originally Posted by rama_bing
    Quote Originally Posted by ajayj
    ESL is a catch all for different tools and languages. you need to be more specific with your question.
    regards
    ajay
    http://edaindia.com/wiki/esl
    Hi thank you for your reply
    my question is
    if
    1.ESL to RTL(using some tool) is possible
    Yes ESL to RTL is possible and is done by almost all ESL compilers.
    Quote Originally Posted by rama_bing
    2.formal verification between esl and rtl is also possible..
    While Formal verification between ESL and RTL is possible I am not aware of any tool which does this. For Commercial formal tools to appear in the market place we would first need a standardization of the ESL languages and the mapping methodology between the ESL code and RTL. As an e.g. take todays equivalence checking tools... They basically breakdown the design to a series of subdesigns where each subdesign is the fanin code of the flop and compare the reference and implementation part of the subdesign In case of ESL tools where there is no hard pipelining defined and the tool inserts registers as per its internal algorithm the above method does not work and some other method has to be found to break the design into more manageable pieces.
    Quote Originally Posted by rama_bing
    then functional verification will happen at ESL level by the designer(not at RTL level).
    That means.. there will not be the need of vmm/ovm etc. is that a bad sign for verification in future?
    Please correct me if I am wrong...
    As I see it VMM and OVM are methodologies and not tied to a specific language. So, even if the implementation language changes, There should be no problem verifying it using the same methodologies as now.

    A second point to consider is that We are used to having our implementation in one language(verilog, VHDL) and the verification code in another(Specman e, Vera, System Verilog, PSL, C, Tcl, Perl etc....) So I dont see a reason why we cannot continue having this divergence between implementation code and verification code in the ESL era

    And finally about formal verification tool, I do not see it replacing dynamic simulation in the near future basically due to the capacity limit of the tool. Moving forward in the ESL era where the design is expected to be even more complex formal tools will have a lot more catching up to do before they can replace the traditional Verification methodologies



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    Re: ESL and Verification

    Quote Originally Posted by shastri.vs
    C to RTL convertion is possible but the code which u get will never be optimized.
    The re is a tool called catapultC which does this. The RTL works file but the u can not meet the design requirements. Even the RTL it generates will not be in readable format. So you cant work on it.
    So OVM or other verification methods are here to stay.
    Shastri,
    I chose to differ about the code quality of C to RTL conversion.... I have personally seen projects executed with various ESL tools and believe that the ESL tool generates code of comparable or better quality. To understand the role played by ESL tools, I would look back in the history of software programming or even HDL's It was traditionally accepted that hand written assembly code to hand written netlist will be always better than any tool generated code. But what one tends to forget is that

    1. This comparison is always between tool generated code and the uber-coder who knows of and makes use of every trick in the book to get the best out of his code. Your average coder always produces code which is comparable to or worse than the generated code.

    2. With time the compiler makes progress and becomes capable of applying different optimization algorithms to bridge the gap between the tool generated code and the uber-coder

    3. While one could generate the best code given infinite resources, Today our designs are getting bigger while our resources and schedule are shrinking. In this scenario even the best programmer would not be able continue keeping pace using the current tools. As an example take your last project you can surely find something in the netlist which could have been better optimized, But would you be able to hand code and optimize the entire netlist and still meet schedule?

    And finally about the code readability part, today when we have already moved from Netlist to RTL we do not care about the readability of the netlist. Similarly when we are ready to move to the ESL tools we would not care about the readability of the RTL code. I know that time has not arrived yet, But it surely will.
    Regards ajay
    http://edaindia.com



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    Re: ESL and Verification

    Dear ajayj,
    I appreciate your optimism.
    C to RTL has to undergo lot of refinement. It will take some time adapt to this new flow.
    But I strongly believe that for Control path design these tools are not useful. For data path its ok. The simulation speed is also very less.
    Lot of work is going on , we have to wait and see.



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