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Yes.. I also want to know. I found some designs use 1'b0 or generated logic_0 (using a DFF) in the same module, but don't undersrtnad what's the difference.
Re: what is logical Tie off cells ?where i can use those ce
The constant 1'b0 or 1'b1 in HDL is realized with a wire connecting to VDD or GND. That is fine until you consider the ESD issue where a gate of a MOS FET is connecting directly to the power supply or ground. That's where the tie on/off gates come in. They are usually provided by the standard cell library and synthesis tool can pick them up automatically.
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