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How to design a frame detect circuit in VHDL

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davidlan

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e1 frame vhdl

Hi.All! Can anybody tell me how to find out a frame code, 6 bytes, from a 77MHz, 8 bits parallel data streaming which not allied. I would rather apreciate an source code. 8O
 

vhdl t1 framer

Make a register 6 bytes wide (or even more) and compare with sync. As soon as you have a match, you are synchronised.
 

xilinx and altera both have reference design, you can search in their web.
 

do it use shift reg.
 

I think it is not need to use a register 6 bytes wide, because it used too many resource to me. thanks "ddt694", i will search it.
 

Try www.opencores.org. There You cam find exampoles of E1/T1 framer in VHDL. May be it'll help You.
 

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