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    $random & $urandon - systemVerilong

    How to pass seed information to $random & $urandom so that test scenario can be reproduced.

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    $random & $urandon - systemVerilong

    function int unsigned $random [ (int seed ) ] ;
    function int unsigned $urandom [ (int seed ) ] ;

    The seed is an optional argument.

    Use the same seed to generate the same sequence of random numbers every time.

    A common practice is to use a plusarg at the command line and read it in the testbench ($value$plusargs) and use it as a seed for the random system tasks.



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    Re: $random & $urandon - systemVerilong

    each time you run a simulation , the seed will be the same!



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    Re: $random & $urandon - systemVerilong

    Quote Originally Posted by anant
    How to pass seed information to $random & $urandom so that test scenario can be reproduced.
    SystemVerilog LRM has a detailed section on random stability to which this question kind of belongs to. It dictates that implementations shall be random stable (under few conditions, see LRM for details). However the $random is not part of it, perhaps b'cos it is part of V2K as well. Also SV adds lot more powerful randomization via class, constraints.

    Ajeetha, CVC
    www.cvcblr.com



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