i2c Start and stop detection

i2c start

Hi all

I am implementing the I2C Slave and I am using the I2C clock SCL for
detecting the start and stop condition . I am detecting the start and
stop successfully in simulation but i am not able to do the same in
the post synthesis scenario. More so I am getting a setup time
violation for the same in the timing analysis . I am running the I2C
at a very slow speed of 100KHz.

The code is below

process (SDA_IN, START_RST,rst)
begin
if rst ='1' then
STARTOP <='0';
-- elsif (START_RST = '1') then
-- STARTOP <= '0';
elsif (SDA_IN'event and SDA_IN = '0') then
STARTOP <= scl;
end if;
end process;
------------------------------------------------------------------------------
-- stop condition detection
process (RST, SCL, SDA_IN, STARTOP)
begin
if RST = '1' or SCL = '0' or STARTOP='1' then
STOPOP <= '0';
elsif SDA_IN = '1' and SDA_IN'event then
if SCL = '1' then
STOPOP <= '1';
end if ;

end if;
end process;

Can any one give me a reliable way to detect the start and stop
condition that the synthesis tool doesnot give any setup time
violation. I am not using a high clock for sampling as the requirement
is to use the SCL only. May be to save board resourse and space.

Help will be appreciated. I am using Altera max II CPLD and the
synthesis tool is quartus 9.0

Thanks

Vipul

i2c start detection

Your posted code is clocking on SDA_IN instead of SCL.

i2c start condition setup time

I have to detect a case when the SCL is high and the data changes from high to low then it is a START condition and when the SCL is high and data changes from Low to High then it is a STOP condition. Henceforth My design and the code is clocked at SDA_IN

Any other way will be greatly appreciated

i2c stop detection

That's how I do it.