FIFO Depth tricky question

fifo depth design

Hi,
I need to provide the delay of 16 clock cycle, using FIFO.
if write frequency and read frequency is same and phase is also same,
then FIFO Depth should be ?
options are :
(1) 16
(2) >16
(3) <16

Thanks for anticipation !!

tagalo tricky question

Your test question is easy, your read and write cycles are synchronous in phase and frequency. Its the old fencepost problem.

Think about when you write to the fifo, and when you need the data to come out 16 cycles later.

I've almost but not quite answered your test question for you.

Deliberately.

min fifo depth same frequency different phase

trekkytekky said:

Your test question is easy, your read and write cycles are synchronous in phase and frequency. Its the old fencepost problem.

Think about when you write to the fifo, and when you need the data to come out 16 cycles later.

I've almost but not quite answered your test question for you.

Deliberately.

Click to expand...

Thanks for ur reply.
thats true, if i take this approch i will get the FIFO depth of 16?
since the frequencies are same i do not need to put the synthronizer, hence synchronizer latency (usually 1 clock cycle)will not be there

Thanks in advance,

fifo depth rules

Here i am assuming write is happening continously.
Read should happen continously but after 16 clocks.
In that case take FIFO DEPTH of 15.
Usually FIFO Full happen after 15 clocks. Check this condition and read the data out.
As soon as Write data is written, read data is read after 16 clock pulses.

Please clarify how data is writing and reading?

Thanks,
Ram

fifo depth question

Can you elaborate more on this.. In my point of view the fifo depth should be 16.

fifo data out depth clock cycle

you can try to simulate to improve your design

depth of fifo

According to your explanation the minimum depth of FIFO is 16. The depth may more than 16. If you use fifo with depth >= 16. Configure "Almost full" with depth 16. Whenever fifo receives 16 words it enables the "almost full" from there you can read the data continuously. For this fifos can be generated easily using "Xilinx Coregen".

Hi guys,

I am sorry to bump such an old thread, but it is just that my answer and logic is different form the ones posted above.
Here is goes...

Well my approach gives me a required FIFO depth of 17....
Because, at the 17th clock period, the first input data (which by now has moved to the 17th position) has yet not been read; hence it needs a memory location on the FIFO during the 17th clock period; and during this 17th clock period it is read off the FIFO and thus vacates it memory location just before the start of the next clock period.

I request anyone reading who is in the know about this topic to please comment on this thread and give a final concrete solution, since we now have all three answers coming up.... and it is very confusing as a beginner.
Hope everyone understands!! :|

There exists a fifo implementation that would work with a depth of 16. For this to occur, the read latency must be 0. This is a "FWFT" fifo -- the data-out port always displays the top of the fifo (when not empty). thus on the 16th cycle, the full flag occurs and the read signal is asserted. The valid data is already on the output. the 16th element is removed from the fifo at the same time the 17th is added and the 15th (now top) is moved to the data out port.

Likewise, a fifo with registered outputs would only need to have a logical depth of 15 -- eg, the full flag asserted when 15 elements are in the fifo. a read at this time would move the 15th element out to a register stage for the 16th cycle of delay.

Because this situation does not make meaningful use of the flow control signals, a shift register is all that is really being implemented. The full/empty/read/write are all just things that you are trying to satisfy to get the desired shift-register. The underlying shift register only requires 16 elements.

Likewise, I'm sure there are also fifo implementations that would require 17 elements to work reliably.