32 bit ADC topology: which is suitable?

32 bit adc

I need to develop a 32 bit ADC (well, 27 bits is enough ). Input ranges from 0 to 10mV (but only 3mV are usable) and at least 20 measurements per second should be possible. I´ve googled a lot and found only 24 bits reliably (and costly) solutions. Input comes from a 350Ω load cell. Good stability, linearity and temperature compensation is a must. Furthermore, as I have a mcu (Atmega164) it needs not to be a single chip version. I´ve tried to use an AD8552 op-amp at the input stage (as a current integrating ampliier) with good results. The whole circuit is included in a feed-back loop chain in order to minimize drifts and off-set. The feed-back loop is controlled by the mcu firmware. It is almost working but I would like to hear more from you GURUS because I know that the topology I´m using is not the only one that could work. Any schematic, even without any explanation, wil be much appreciated.

32-bit adc

I have checked some numbers:

For 10mV range and 27bit resolution the LSB is

10e-3/2^27=74.5pV (PicoVolt!)

The noise from source resistance is

sqrt(1.66e-20*350*(pi/2)*20)=13.5nV (NanoVolt!)

To have a 1LSB differentiation at 27bit every 50ms you need a timing measurement clock of

50e-3/2^27=372.5ps

for an 1bit feedback reference system (Sigma-Delta-DAC)

Consider that the Seeback-Effect gives between 7uV/K and 32uV/K depending on metal combination. So the temperature stability should be

13.5nV/7uV/K=1.9mK (MilliKelvin!)

over 50ms.

Could you explain the meaning "topology could work"?

32bit adc

where in the world would get a reference voltage for this ADC?
even NCST would not have such a stable reference.

hock

adc 32 bit

Thank you rfsystem. Your calculations seems to be right. I´m achieving nearly 25 bits resolution by now. The topology I´m using is a modified ΣΔ continuous time integrating system running at 300 samples per second and followed by two FIR filters. The system doesn´t use a voltage reference. Instead, it´s gain and zero stability depends only on the ratio of two resistors (their absolute value are of no importance). I know there are some equipments on the market that claim to do more than this, e.g. **broken link removed** and wonder what is the type of converter are they using to achieve this.

adc topology

I did not found a Keithley 2200. I think that the Agilent 3458A is the current state of the art.

**broken link removed**

If you take a look at page 11 ther is a diagram showing reading resolution versus reading frequency and a table right beneath.

The 3458A have 18bit at 10us. That mean for an integrating with 1bit-DAC (a +- reference switch)

10e-6/2^18=38.15ps
1.4e-6/2^16=21.36ps

to select 2 cases. It is unrealistic that they using a 50GHz clock to determine the timing of some proprietary ramp methods. I guess that that the feedback is a DAC with some number of bits. That rises the linearity issue which is avoided for 1Bit-DACs. So calibration is needed.

Could you draw your topology?

Sorry I misread the Keitley number. That seems the right one

http://www.keithley.com/data?asset=5799

The reading vs. resolution is similar to 3458A

167e-6/2^19=31.85ps

32 bit adc

My system uses a 16 bits PWM DAC feedback (that´s the modification with respect to the conventional ΣΔ circuit) and it looks like the attached file (this is not the final circuit). The large number of resistors in the feedback chain are very stable ones. It needs calibration for sure and it also auto-zeroes for small and low frequency variations. The input signal is almost allways ZERO and never goes out of this situation for more than a few seconds, so the auto-zeroing principle is very effective. The ramp generator shown at the bottom of the circuit has nothing to do with the linearity of the converter. It is used only to get some output from the DAC. The DAC output is correct when it balances the input current from the load cell. The input multiplexer is used to null the off-set voltage of the whole system. The circuit originated from the one I´ve found in a wheighing scale (see attached file)