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Help me! The stratix III is unstable

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unimelb

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unstable fpga design

Hello, I am a new comer in FPGA. Currently I coded a verilog module for my project but there may be something wrong because after I adding it into my project the system becomes unstable. Is it caused by too many state machines? Or is there something wrong with my coding style? Thank you!
 

Seriously, you can't exspect an answer to your question without giving some more information about the purpose and operation of your code. You also may want to elaborate, what "becomes unstable" actually means.

As a - very general - answer: If the code synthesized correctly and no problems are indicated in timing analysis, I suspect rather a problem of inadequate algorithms than coding problems.

To disprove my (possibly destructive) assumption, you should be able to clarify, why and how the code is able to perform satisfyingly by design.
 

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