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Why do we need Verilog-A? Any reason is welcome.

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abcyin

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Hi, all

I am a freshman in Verilog-A, I am wondering why do we need verilog-A, any reason is welcome here, from fundamental to specialized, finally I will summarize your replies in this post.

Thanks in advance,
and best regards.
 

1. if you use verilog-A model instead of the real schematic,the simulation time could be reduced.this could help you verify your system very efficiently.
 

and you can easily use verilog-A to build define an analog circuit block like controllable delay line, filter and stuff, and use it in your system level simulation without even having the circuit. so that you can quickly evaluate your system performance and define specs for each components.
 

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