fallingrain_83
Junior Member level 1
Help PLZ!! FPGA Clock
Hi all
I want to creat a clock from the input clock that has less frequency
I tried this, however it is not working
module(clk,...)
input clk; // connected to C9 pin of Spartan3 XC3S200
reg [0:25] count;
reg clk2;
allways @(posedge clk)
begin
count<=count + 1;
clk2 <= count[25];
end
allways @(clk2)
begin
clk2<=0;
,.....
end
Hi all
I want to creat a clock from the input clock that has less frequency
I tried this, however it is not working
module(clk,...)
input clk; // connected to C9 pin of Spartan3 XC3S200
reg [0:25] count;
reg clk2;
allways @(posedge clk)
begin
count<=count + 1;
clk2 <= count[25];
end
allways @(clk2)
begin
clk2<=0;
,.....
end