Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

pwm and one bit dac in verilog

Status
Not open for further replies.

semesu

Newbie level 4
Joined
Dec 23, 2008
Messages
7
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,337
dac verilog code

Hi,
I have a project on pwm in verilog programming language. "pwm and one bit dac". The aim of this project is to convert the dıgıtal data to analog. Ihave found codes.
I am usıng xilinx spartan 3E kit

module PWM(clk, PWM_in, PWM_out);
input clk;
input [7:0] PWM_in;
output PWM_out;

reg [8:0] PWM_accumulator;
always @(posedge clk) PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;

assign PWM_out = PWM_accumulator[8];
endmodule



but,in the codes a pwm accumulator is mentıoned and there ıs a command it is"PWM_accumulator <= PWM_accumulator[7:0] + PWM_in;" I don't understand why this command is written in the program and what is the functıon of the pwm accumulator?
my second questıon is what does the samplıng frequency mean?there are some explanatıons on the ınternet but I don't understand them.
ıf there is anyone to help me,I will be glad.
thanks
regards
 

1 bit dac+pwm

The code represents a first order delta-sigma modulator. It involves an integrator respectively the said PWM_accumulator. I see two options: Learn from a text book about delta-sigma principle or perform a numerical simulation with some input data (you can do it by pencil and paper method) and watch the results.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top