Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

lvcmos33 io maping fails while lvcmose 25 pass(ise8) why???

Status
Not open for further replies.
G

gauz

Junior Member level 3
Joined
Jul 18, 2005
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,537
lvcmos25 lvcmos33 group:comp.arch.fpga

I implement a design in spartn3, and set the io standard to lvcoms33(or lvttl) but it always fails in mapping "ERROR:pack:1655, the timing-driven phase encoutered an error".
if I change the io standard to lvcmos25, then it pass.
Dose anybody know what's the problem?
Thanks in advance
gauz
 

lvcmos33

gauz said:
I implement a design in spartn3, and set the io standard to lvcoms33(or lvttl) but it always fails in mapping "ERROR:pack:1655, the timing-driven phase encoutered an error".
if I change the io standard to lvcmos25, then it pass.
Dose anybody know what's the problem?
Thanks in advance
gauz
Click to expand...

The voltage thesholds for LVCMOS25 and LVCMOS33 are different. Possibly signals are failing their setup and hold times? Can you specify a slower clock before you compile?

Alternatively, are you trying to specify LVCMOS33 on a bank which does not support it?
 

error:pack:1654

Thanks for Pootle's reply.
I slacked the clock frequency but the same error occurs.
I leave the io location no specified and the io standard is still lvcmos33, it pass too.
it's really a puzzling bug, no more hint from ise tool but the "ERROR:pack:1654 - The timing-driven packing phase encountered an error."
if I uncheck the option "performing timing-driven packing and placement" then the Map stage could pass but fail in routing saying no all net are routed.
is it possible a bug from ISE?

Added after 5 hours 32 minutes:

Bug fixed, due to several no specified ports lockation which I am not finally determined.
I had thought if I don't specified the port location, the tool will automatically assign an available location to the port, but why it doesn't?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top