Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Explain me the calculation of minimum clock period

Status
Not open for further replies.
V

vikram789

Member level 3
Joined
Aug 1, 2008
Messages
59
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
1,671
in the attached file in calculating min clock period, the propagation delay of and gate is neglected in Q1 to Q2 path and calculation is done from t(pd) of D FF.similar thing is done in Q2 to Q1 path. plz explain the reason for it
 

Re: min time period

what will be the change if a gate is joined after the JK FF
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top