ASIC_intl
Banned
How important is the check_design command for synthesis?
After doing check_design I FIND THERE ARE SOME PROBLEMS IN MY DESIGN. The report generated after check_design contain name of some instances and also nets that are not present in the design file. I am using the check_design command before compilation. How to see these problems whose correponding instance and net name are not present in the RTL which ere analyzed and elaborated.
After doing check_design I FIND THERE ARE SOME PROBLEMS IN MY DESIGN. The report generated after check_design contain name of some instances and also nets that are not present in the design file. I am using the check_design command before compilation. How to see these problems whose correponding instance and net name are not present in the RTL which ere analyzed and elaborated.