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Doubt about two technologies..

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sp3

sp3

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Hi guyz,

I have simple basic doubts. Please clarify :

1. Can we have two different blocks (say one analog and one digital ) processed of two different technologies say 90 nm and 60nm on a single ASIC chip ? I got this doubt when I heard this someone saying, technology wise Analog is slower than digital.

2. Can we have two different blocks processed using two different number of layers ( say one with 4 and another with 6) on a single ASIC chip ??

Thanks,
sp3 :|
 

1st question : Yes,why not ? at least you can easily see its posibility in the back-end process when we have to concatinate more than 2 submodules to form a chip. In front-end, i think it also possible but the interconnections between 2 submodules must be manually mapped by you in stead of by Design Compiler in any homogenous design.
 

Is it possible to fabricate 2 modules which are based on different technologies?..

This is the first time I came to know..

Guys, If possible please elaborate..
 

I think it is possible there are 65nm transistors and 90nm transistors in a sigle chip, but that doesn't mean two technologies.
and I realy don't know two different technologies can be in a chip, develop the two different technologies at the same time.
for different technology, there are different space rule, different thickness metal, different dope rate, different layer and material and so on
so I don't think it is possible.
are you sure?
maybe some guyes from foundry such as TSMC can answer me.
 

This is a Patent Info, that we can fabricate two different modules with different process tech on same die.
Probably this could be true in future, but as pf now it is not possible to process two different tech on single wafer.

what ppl mean by analog is slower than digital -->
Charaectrazation for analog blocks and design is tedious job as compare to digital where we have STD CELL Lib. characterized for given technology ( process). So offen on chip ( SOC) we will be using lets say .13 u digital cell library, then we might not able use minimum sized transtors ( L = 0.13 u) in analog blocks, but it is of higher dimensions.
but processing and all ( layers, recipies) are same as 0.13 process.

hope it helps
 

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