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about dso.ADC high speed sample,but low store in sram

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alphi

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I design a digital oscilloscope,use a 100MHz AD converter ADC08100,ADC08100 can not work below 20MHz sample rate.
but i need slow sample rate,such as 5MHz,1MHz,200KHz.......So I think use 100Mhz clock to sample,and use slow clock(ex.5MHz)
to store sram,equal every 5 sample only store one data.

so I use a clock syncronizer to syn two domin clock,but clock syncronizer is not completely remove mestastable stage.if it
occur mestastable stage,the address generator will generate error address.

anyone have another method to realize high speed sample and slow store.
 

Hi,
Due to which factor the limit on low sampling rate is caused?

By the way, what if you put a prescaler to the address counter of the SRAM?
Regards,
Laktronics
 

I can not only use prescaler to AD converter clock,because ad converter can not work below 20MHz,so I need maintain ad converter clock >20Mhz,such as 100MHz,then use prescaler to generate slow clock for sram.
 

Hi,
I think I got your requirement, I was only suggesting to use a prescaler for the clock going to the address counter and not to A/D converter. Instead of using a separate clock for the address counter use the same clock going to AD, prescale it and give it to the address counter. The RAM write pulse may be generated by decoding the prescaler output. Any problem?

Regards,
Laktronics
 

thank laktronics
your suggest is another method, if I use this method: use still 20MHz clock to AD converter,then use prescale clock to address counter.because i need about 12 type sample rate:10M,5M,2.5M,1.25M ...,so i need a mux to select difference clock to address counter,the counter will generate large delay,this delay will make sram data input is not sync with write clk.

Added after 22 minutes:

delay of much channel mux is too large
 

Hi,
I know that at these frequencies, delays are critical and things are not that easy. But, won'tyou get a time of clock period minus coversion time to strobe the data?, which in case of 20MHz will be (50nsec - 8.9 nsec ) + 4.4 nsec ( data hold time into the next rising edge).

Since you are willing to throw off so many samples, there may be even better methods to pick up one sample from each set, may using memory stack/buffer loaded with only half the samples from ADC so that you will get more time to take care of your delay?

Regards,
Laktronics
 

thanks you.
maybe i can try to use a 2:1 circuit to divide ADC output into half,from 20MHz data divid into 10MHz.it will give me more time to take care of delay.
 

If only problem is that you shoud use ADC08100, which can't work properly with sampling rates below 20MSPS you shoud use only a some 8 bit latch. You shoud simply write on latches every second, fifth, 10th etc sample. You just need to generate proper strobe signal, which will drive Enable pin of the latch.
 

Moss,
if use this method,the latch's D input port is not sync with low frequency clk pin.
 

Some details of the design haven't been mentioned at all, e g. the maximum speed address counter + RAM can be operated, and if additional operation modes are intended with the circuit. But from what's been said, I basically don't understand, why the RAM control is synchronized to fast clock instead of AD data only? If I want to acquire a digital signal at a lower rate, I down-sample the signal, that's all. Additionally, a decimation filter may be used for noise reduction.
 

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