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Modeling the transmission line during simulation

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azerty.t

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Hello,
can someone help me how should I model the transmission line of an LVDS driver under cadence environnement. There is an instance called ( tline ) in ( analogLib) but I don think it s the appropriate one and I don t know what should I put as parameter with this tline . My Lvds will link an ASIC to an FPGA with a distance of about 20cm.

Regards.
 

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