How to do clock gating with several enable signals

Hi all,

I am new to this ASIC design.

I want to use clock gating to reduce power. But i am wondering how should i use clock gating for a module that has several enabling signals to do certain operation.

For example, for this DACReg module, it has enable signals:

1. Load_1 for loading data
2. Load_2 for initializing data
3. Prog2, Ecs and up_down for counting and shifting operation.

So how do i do clock gating with these enable signals that is activated for certain operation.

I will use Power compiler to do this clock gating but has still to figure out on how to implement this clock gating circuit.

Another thing, usually how many gate counts that is needed in order to efficiently implement this clock gating circuit?

Currently, for my datapath design, i have several flip flop and latches:

1. LReg (9-bit latches)
2. WReg (8 -bit latches)
3. Pol ( 1-bit FF)
4. Flag_hot ( 1-bit ff)
5. Flag_actv ( 1-bit ff)
6. Current_on (1-bit ff)
7. DACReg (5 -bit ff)

I plan to use clk gating circuit for each module listed above. So is this OK? Or is the number of latches and flip flop too few to implement clock gating cct?


Hope to get response from the experts here.

thanks
enoorsal