adrianos
Newbie level 4
Ok I've read through lots of posts regarding noise isolation and guard ring strategies and I like to add some import points:
Without doubt the one thing that layout people get wrong is guard rings. Very wrong in fact. Let's look at some examples:
1. What potential do I tie the inside of my guard ring to? i.e. the ptap connection
- Local ground?
I've seen this done lots and lots of times. But what are you actually doing
when you do this?
So you've went through all the trouble of creating guard rings and now you've
just shorted them out by coupling all the noise in main p-substrate to you're
(supposedly) quiet substrate.
You absolutely NEVER tie inside the guard ring to outside the guard ring.
Therefore there must be a different tap for the 'quite' p-subs. e.g. VSUB.
So a good strategy is to have VSUB(quite) and VSS(noisy) star-connected
back to a pad. Better still if you can have two package pins and two bond
pads!
2. Another important question is what potential do I tie the NWELL quard ring to?
- VDD?
Again I've seen this done lots of times. If you tie the nwell guard ring to vdd,
i.e. the same vdd that all the active (noisy) devices share, then you've just
coupled all that noise INTO your (supposedly) quite substrate. So the
very thing you were trying to negate you have in fact made worse.
Again you need a quite potential for the nwells.
So to summarize a good strategy for guard rings:
A separate (quite) potential for the substrate inside the guard ring and a separate
(quite) potential for the nwell itself.
Hope this helps,
- Aio -
Without doubt the one thing that layout people get wrong is guard rings. Very wrong in fact. Let's look at some examples:
1. What potential do I tie the inside of my guard ring to? i.e. the ptap connection
- Local ground?
I've seen this done lots and lots of times. But what are you actually doing
when you do this?
So you've went through all the trouble of creating guard rings and now you've
just shorted them out by coupling all the noise in main p-substrate to you're
(supposedly) quiet substrate.
You absolutely NEVER tie inside the guard ring to outside the guard ring.
Therefore there must be a different tap for the 'quite' p-subs. e.g. VSUB.
So a good strategy is to have VSUB(quite) and VSS(noisy) star-connected
back to a pad. Better still if you can have two package pins and two bond
pads!
2. Another important question is what potential do I tie the NWELL quard ring to?
- VDD?
Again I've seen this done lots of times. If you tie the nwell guard ring to vdd,
i.e. the same vdd that all the active (noisy) devices share, then you've just
coupled all that noise INTO your (supposedly) quite substrate. So the
very thing you were trying to negate you have in fact made worse.
Again you need a quite potential for the nwells.
So to summarize a good strategy for guard rings:
A separate (quite) potential for the substrate inside the guard ring and a separate
(quite) potential for the nwell itself.
Hope this helps,
- Aio -