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Declaring a variable as output in two different modules in Verilog

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research_vlsi

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whether its possible to declare a variable as output in two different module?
(In verilog)
 

Re: verilog doubt

What's the intended behaviour of the output? If the output is treestatable, an enable signal must prevent simultanous activation of both drivers to the output. Then a multiplexer is inferred from the code.
 

Re: verilog doubt

Hi FvM

Thnks for ur comment.

am working with three modules (m1, m2,m3) in a project. while running the code either m1 or m2 module will work.(any one only will work) the ouput variable from m1 or m2 module will enable m3 module.

i used same variable name for the enable (as output) in m1 and m2 module. but i didnt get correctly, during simulation its going wrong.

whether i should use different variable name in m1 and m2 or whether its possible to use same name.
 

Re: verilog doubt

Hi !
Assuming module m3 works from the output of either module m1 and m2.I think its absolutely possible to put the output of m1 or m2 ans input to m3.make sure to declare the m3 port as bidirectional port
 

Re: verilog doubt

Hello,

the important thing is, that the respective outputs of the inactive moduls must be tristated, outx = 1'bz.

However, for a clearer functionality, you should better use a multiplexer at the top level, using assignments in a case or if construct.

Regards,
Frank
 

Re: verilog doubt

thnks for the reply..

I will try these ideas..
 

verilog doubt

U can use same variable as output in m1 and m2.
i dont see any problem.
Could u pls tell us! what prob u facing?

any error or unexpected behaviour?
 

Re: verilog doubt

hi shiv_emf

ya i got error in simulation, due to declaring same variable as output in two different module i cant get correct value..

comments pls
 

verilog doubt

you should get an 'x' in simulation because of the multiple drivers from both the modules driving ur top module.
Better to have control at the top level as suggested earlier.
 

verilog doubt

wht is the error research_vlsi ?
 

Re: verilog doubt

i got 'X' for that output variable. actually i should get '1'. thats the error
 

verilog doubt

ok ...

R u tryiing all combinations of values for o/p of m1 and m2 ??

suppose if u use different variables for m1 and m2. in that case ......R u getting expect behaviour?
 

Re: verilog doubt

if i use different variable for the m1 and m2 module, am getting correct behavior.
 

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