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DFF max operating Frequency

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master_picengineer

master_picengineer

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Dear all,
I designed a flip flop using Virtuoso and I simulted it. It work perfectly, however I don't know what is the maximum frequency that it can support. Have I to determine this Maximum operating frequency by simulation or there is another technique to do it ?
Thanks in advance for your replies.
 

simulation, i guess u need to put some spec on it, like Vhigh,Vlow, Trise , Tfall, then try to find by simulation the maximum freq. and load
 
Thanks Safwat for your reply,
In fact I wanna reach the maximum performance of this dff. I know only that
Vhigh=1V, Vlow=0V
The thiks that I like understand is:

1- According to what and how to chose TFall, Trise for a certain frequency ?
2 Hold up and set up Times ?

Please help.
 

well, i THINK that this is usually dependent on the clock frequency, also the kind of application this dff is used in.
like if u are talking about multi-phase clock generator used in ADCs then the trise and tfall have to be lower than a certain limit not to violate the non-overlapping clock condition and also not to cut from the allowed period for the OTA to settle.
 
Yes indeed.
let suppose that I determined hold up and setup time as well as the maximum frequency by simulation. Suppose for exemple Fmax=1 Ghz. How should I fix Tfall, and Trise ?
5% , 10 % of the period ?
 

You can try that
1 - any Tfall and Trise
2 - real Tfall and Trise
 

Remember that, depending on the design, the fall and the rise time of the input clock and the input data can effect setup and hold times. When the clock has a large rise time, usually setup and hold times will have to be larger also. My advise is to simulate using real components to drive your DFF instead of ideal voltage sources.
 

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