free_electron
Junior Member level 2
all right . here is question two for today.
i am looking for a verilog simulator that allows me to do the following:
preload registers !
assume you have a block that you need to test,. the signals in this block come from aregisters that are mapped onto an address/daatbus and control signals.
with a normal simulator you need to write a whole bunch of code to preload all these registers ( you need to go through the motion of setting the address , setting the data , setting write enable , then giving a clock edge , then changin address and data , etcetera etcetera etcetera. it even gets wors if you can only supply waveforms. then you need to draw all that stuff out by hand. lets say you have a block that needs 32 registers set up before it can do anything.
It would be great if you can simply write in the simulator testbench something like
this would save all the time of mucking around by twiddling all these input signals to get the registers loaded to some specific setting so you can simulate a specific case.
anyone know of a simulator that can do that ?
then on to the next question. i want a simulator that i can single step ...
clock - clock - clock -clock. Every time the thing is in break, i can examine the register contents in realtime . Aldec Active-HDL has such a feature. You can set breakpoints in the simulation, and then single step. you can examine the contents of all registers and the level of any node in the entire design ( you can set watchpoints and the like .
The only thing that is missing, is actually: at that time change the contents of a flipflop. For some reason they forgot that. This would be really powerful.
You put the simulation in break, see that some register got loaded wrong : you can correct it and continue the sim. no need to fix the source and resynthesize.
Now you first have to fix that problem and then can go on to the next ... everytime you need a restart. Very frustrating if the problem occurs only at like the 500 millionth clocktick in the simulation ... ( i got 64 bit counters.. and when they reach some large number it screws up ... ouch... simulation times up the wazooo , yes i could provide some extra 'debug logic' so i can preload, but then i also need to provide that debug logic to all other 30.000 flipflops in the rest of the system. no way ...)
Then the next thing that i want is to be able to save the state of all registers in the design.
so : you put a breakpoint jut before where it goes wrong. take a 'snapshot' of all register contents and save to file. When it screws up :change the logic, resynthesize , reload the register snapshot into the registers and bam , 1 clocktick later you know if it is solved or not.
Or even you don't have to resynthesize: suppose you find out that the cause is that somewhere a register got corrupted : you reload the snapshot , set that register correct and continue. You can then later fix the code. But in one sim sweep you can find multiple problems and you only need one edit and re-synthesize. This would be a tremendous time saver. Especially when the synth times start to become in the order of 5 minutes to half an hour and more ... and the sim times also run half an hour and more ...
So : which tool can do that ? No-one ? it's almost 2008. time we get some stuff that works.. software programmers have had that capability for years. Time for the 'poor' hardware designers to get the same capability.
i am looking for a verilog simulator that allows me to do the following:
preload registers !
assume you have a block that you need to test,. the signals in this block come from aregisters that are mapped onto an address/daatbus and control signals.
with a normal simulator you need to write a whole bunch of code to preload all these registers ( you need to go through the motion of setting the address , setting the data , setting write enable , then giving a clock edge , then changin address and data , etcetera etcetera etcetera. it even gets wors if you can only supply waveforms. then you need to draw all that stuff out by hand. lets say you have a block that needs 32 registers set up before it can do anything.
It would be great if you can simply write in the simulator testbench something like
Code:
// startup code goes here that sets up the reset etc
loadregs
my_register = h55
my_control = so and so
// all other registers get preloaded here
endload
// now follows the rest of the testbench.this would save all the time of mucking around by twiddling all these input signals to get the registers loaded to some specific setting so you can simulate a specific case.
anyone know of a simulator that can do that ?
then on to the next question. i want a simulator that i can single step ...
clock - clock - clock -clock. Every time the thing is in break, i can examine the register contents in realtime . Aldec Active-HDL has such a feature. You can set breakpoints in the simulation, and then single step. you can examine the contents of all registers and the level of any node in the entire design ( you can set watchpoints and the like .
The only thing that is missing, is actually: at that time change the contents of a flipflop. For some reason they forgot that. This would be really powerful.
You put the simulation in break, see that some register got loaded wrong : you can correct it and continue the sim. no need to fix the source and resynthesize.
Now you first have to fix that problem and then can go on to the next ... everytime you need a restart. Very frustrating if the problem occurs only at like the 500 millionth clocktick in the simulation ... ( i got 64 bit counters.. and when they reach some large number it screws up ... ouch... simulation times up the wazooo , yes i could provide some extra 'debug logic' so i can preload, but then i also need to provide that debug logic to all other 30.000 flipflops in the rest of the system. no way ...)
Then the next thing that i want is to be able to save the state of all registers in the design.
so : you put a breakpoint jut before where it goes wrong. take a 'snapshot' of all register contents and save to file. When it screws up :change the logic, resynthesize , reload the register snapshot into the registers and bam , 1 clocktick later you know if it is solved or not.
Or even you don't have to resynthesize: suppose you find out that the cause is that somewhere a register got corrupted : you reload the snapshot , set that register correct and continue. You can then later fix the code. But in one sim sweep you can find multiple problems and you only need one edit and re-synthesize. This would be a tremendous time saver. Especially when the synth times start to become in the order of 5 minutes to half an hour and more ... and the sim times also run half an hour and more ...
So : which tool can do that ? No-one ? it's almost 2008. time we get some stuff that works.. software programmers have had that capability for years. Time for the 'poor' hardware designers to get the same capability.