Discussion on two importat constructs in system verilog

system verilog prioirty

Hello freinds
I am learning system verilog. I am following system verilog for design by chris spear. I didnt understand the concept of two important constructs. UNIQUE and PRIORITY. I want a indepth discussion on those. Your help is appreciated

Thanks and Regards
Deepak

Deepak,

The key-words “unique” and “priority” are part of the SV language, used with if-else/case statements. They are not only the directives for synthesis tool, as in Verilog. The “unique” is replacement for “parallel_case” and “priority” is replacement for “full_case” synthesis directives. They will be interpreted same by both simulator and synthesis tools.

Even these key words won’t guaranty us about not generating any latches. Because, if you are assigning two outputs in the case/if-else statements, there is a chance that you will not assign both outputs in each and every case/if-else branch, which will lead to generation of latches, even with priority. Finally it boils down to be responsibility of designer’s to think and code.

For more information, read –
www.sunburst- design.com/papers/CummingsSNUG2005Israel_SystemVerilog_UniquePriority.pdf

-mkrishnap

Hi

im also planning to learn SYSTEM VERILOG please send me some file it would help me lot to read


thanx......in advance

sativlsi@gmail.com

Hi Satish,

The folowing PPT will be helpful for beginers in SV. Anyways, if you 're proficient in verilog & C, understandnig the SV concepts is not a big deal...But how to utilise them in the real-time projects...is more important...

www.systemverilog.org/pdf/SV_Symposium_2003.pdf

-mkrishnap