nag123
Member level 1
modelsim invisible waveform
Hi all,
I am new to verilog. I have implemented a mux and testbench in verilog. I simulated the design. but no signal is displayed in object window to watch. I couldn't even see the mux component instantiation. Can you help me?
Here is the code
module mux(q, in1, in0, s);
output q;
input in1, in0, s;
wire tmp;
assign q = in1 & s | in0 & (!s) ;
assign tmp = in1 & s;
endmodule
module top;
wire q;
wire in1,in0, s;
reg in1i, in0i, si;
mux mux0(.q(q), .in1(in1i), .in0(in0i), .s(si));
initial
begin
in1i = 1'b0;
in0i = 1'b1;
si = 1'b0;
end
always
begin
#10 in1i = !in1i;
#50 in0i = !in0i;
#20 si = !si;
end
assign in1 = in1i;
assign in0 = in0i;
assign s = si;
endmodule
Hi all,
I am new to verilog. I have implemented a mux and testbench in verilog. I simulated the design. but no signal is displayed in object window to watch. I couldn't even see the mux component instantiation. Can you help me?
Here is the code
module mux(q, in1, in0, s);
output q;
input in1, in0, s;
wire tmp;
assign q = in1 & s | in0 & (!s) ;
assign tmp = in1 & s;
endmodule
module top;
wire q;
wire in1,in0, s;
reg in1i, in0i, si;
mux mux0(.q(q), .in1(in1i), .in0(in0i), .s(si));
initial
begin
in1i = 1'b0;
in0i = 1'b1;
si = 1'b0;
end
always
begin
#10 in1i = !in1i;
#50 in0i = !in0i;
#20 si = !si;
end
assign in1 = in1i;
assign in0 = in0i;
assign s = si;
endmodule
