sul
Newbie level 5
Hi,
I am trying to implement altlvds_rx mega function in Quartus 3.0.
The requirement is input line(to be de-serialized) receiving data at 300Mbps and another input signal "Start".
Only when "start" is asserted I need to start deserializing. Deserializing factor is 8.
The problem is if I use the pll_enable pin, connected to Start. After enabling the pll_enable it takes some clock cycles for the output clock to get locked and I loose some of the input bits.
Also data_align does not work, since it essentially just shifts the output by 1 bit.
Any help will be highly appreciated.
-Sul
I am trying to implement altlvds_rx mega function in Quartus 3.0.
The requirement is input line(to be de-serialized) receiving data at 300Mbps and another input signal "Start".
Only when "start" is asserted I need to start deserializing. Deserializing factor is 8.
The problem is if I use the pll_enable pin, connected to Start. After enabling the pll_enable it takes some clock cycles for the output clock to get locked and I loose some of the input bits.
Also data_align does not work, since it essentially just shifts the output by 1 bit.
Any help will be highly appreciated.
-Sul
