finger number and multiply value?

Hi,
In layout, is it an obligation that finger number must be matched with "Multiply" values of transistors in schematic?

yann_sun said:

Hi,
In layout, is it an obligation that finger number must be matched with "Multiply" values of transistors in schematic?

Click to expand...

I didn't get your point clearly, but the reason why they make the transistors in fingers is to allow the construction of the MOS into a compact array(IC real estate purpose).
also by fingering the MOS will give you less parasitic resistance.

And Multiplier is only to let the devices how many times you're going to use it.

cheers

yann_sun said:

Hi,
In layout, is it an obligation that finger number must be matched with "Multiply" values of transistors in schematic?

Click to expand...

hi,
i think,for each mos transistor, she can have its own finger number, e.g for mos transistor with W=10,L=1, in layout, she can be 5 fingers with w=2.
and i think, finger number is for layout design, and multiply value for schematic.
also, finger number if for one transistor, and multiply is for many transistors with the same size.

correct me if i'm not right.
jeff

It does matter in design!!
The more fingers you put in layout, there is an impact on the parasitic gate resistance and capacitances. So plz consult your designer before you change the number of fingers/multipliers you do in your layout..

There are some parasitic RC difference between multiply and finger number. But it is not very much between PEX and simulation result in usual design. Some PDK calculate the sum multi = finger number × multi.

for ESD transistor rules, I think finger number no less than multiply value!

The multiplier value is added to estimate the parasitics that will occur during layout.
It is not necessary to mach the multiplier value in the schematic to the number of fingers in the layout (your Layout will still be LVS clean) but the parasitic estimates might change. If you are a layout engineer, talk to the designer abt it and the parasitic changes the design can tolerate.

--cmos_dude

check razavis book i think it is depends on noise figure

hi all,

i think,for each mos transistor, she can have its own finger number, e.g for mos transistor with

W=10,L=1, in layout, she can be 5 fingers with w=2.

and i think, finger number is for layout design, and multiply value for schematic.

also, finger number if for one transistor, and multiply is for many transistors with the same size.


thanx.

Hi all,
I think the multiply is for estimating the parameter, but the figure is for reducing the parasitic resistor.Is it ?

For LVS it doesn't matter but for design it does. If you use multipliers in the schematic then for simulation the full drain and source area will be given in the netlist. It will only be treated as if there were N identical full transistors. If you use fingers in the schematic then it should calculate the reduced source/drain area for the simulation but this might depend on the PDK. Of course for layout the difference is obvious regarding size and parasitic capacitance.

As far as changing a 10um transistor with 2 fingers to a 5um transistor with 4 fingers that depends on the application. For matching you should at least make sure that the matching transistors still have the same finger width so you can do common centroid or simple matching or what ever is required.