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Modeling clock with jitter in Verilog

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beowulf

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verilog clock jitter

How is clock generated for a verilog simulation model with jitter. Any papers or books will be useful.
Is there a standard way to do this?
How frequently are such clock models used?

Thanks,
Beo
 

verilog a jitter clock

At the simulation level I dont think you would need to take into consideration the clock jitter. May I know exactly what are you trying to do by giving this information to your simulator.
 

clock jitter verilog

This is a high speed serial bus, one of the end modules talks with a serializer and then to PIPE.

Trying to find out if there can be any problems before the design is put on board.

Do let me know if any such clock models are available in verilog or a HVL

Thanks,
Beo
 

verilog code clock jitter

Below Testbench code is an example way of generating jittery code for sims.

// initialize
initial begin
force clk = 1'b0;
// wait for sometime...
#400;
// release forece
release clk;
end

always @()
clk <= #(period/2+$random(-jitter/2,jitter/2) ) ~clk;
 

verilog-a clock jitter

Hi rjainv,

Have you tried simulate this piece of code?

I tried simulate it using ModelSim and it failed.

Error: $random too many argument

However, I have fix it and below is the code:

Code: 
// clock jitter simulation 

module clk_jttr ();
    
    reg clk;
    
    parameter period = 20;
    parameter jitter = 4;       //will generate random value between -4 to 4
    
    // initialize
    initial begin
       force clk = 1'b0;
    
       // wait for sometime...
       #200;
   
       // release force
       release clk;
    end

    always 
    #(period/2 + $random %(jitter)) clk <= ~clk; 
    
endmodule

Hope it helps
Enjoy!
 
verilog jitter

Thanks no_mad,

I didn't try to simulate it... just came from top of my head... was intended to be an outline...
 

jitter verilog modeling

Thanks guys...!
I would still like to know if therer is a standard way to model this...

Thanks for the suggestions and pointers...

Beo
 

more version with +/- jitter

Code: 
parameter jitter = 2000;  // ns x 1000 
integer seed;

always #(80+$dist_uniform(seed,-jitter,jitter)/1000.0) clk0=~clk0;
 

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