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problem with testbench

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ghostridergr

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well this is my testbench:
Code:
library IEEE;
use IEEE.std_logic_1164.all;
use STD.TEXTIO.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;


entity tb_file_sum_square_dif is
  generic
		(
			N :integer := 8
		);
end tb_file_sum_square_dif;


architecture TB_ARCHITECTURE of tb_file_sum_square_dif is
file IN_VECTORS: TEXT open READ_MODE is "input.txt";
file OUT_VECTORS: TEXT open WRITE_MODE is "output.txt";
--here
component sum_new_squaredif_n
    port(
     a,b: in signed(N-1 downto 0);
	   sum:out std_logic_vector(3*N-1 downto 0);
	   borout:out std_logic); --dn kserw posa einai to worst case
end component;

signal a,b: signed(N-1 downto 0);
signal sum:std_logic_vector(3*N-1 downto 0);
signal borout: std_logic;
begin
    UUT: sum_new_squaredif_n
        port map (
          a=>a,
          b=>b,
          sum=>sum,
          borout=>borout);
            
    process
        variable IN_BUF: LINE;
        variable OUT_BUF: LINE;
        variable a_var,b_var : bit_vector(N-1 downto 0);
        variable sum_var:bit_vector(3*N-1 downto 0);
    begin
        
        while not ENDFILE(IN_VECTORS) loop
            READLINE(IN_VECTORS,IN_BUF);
            READ(IN_BUF,a_var);
            READ(IN_BUF,b_var);
        read_inp: for k in 0 to N-1 loop
              a(k)<=to_stdulogic(a_var(k));
              b(k)<=to_stdulogic(b_var(k));
              end loop;
              wait for 1 ms;
            WRITE(OUT_BUF,STRING'("SUM OF SQUARE DIFFERENCE IS= "));
           -- sum_var:=to_bitvector(sum);
            WRITE(OUT_BUF,to_bitvector(sum));
            WRITELINE(OUT_VECTORS,OUT_BUF);
        end loop;
        --wait;
    end process;
    
end TB_ARCHITECTURE;
and these are my warnings:

Code:
 Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 0  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 0 ns  Iteration: 1  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 1 ms  Iteration: 1  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 1 ms  Iteration: 1  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 2 ms  Iteration: 1  Instance: /tb_file_sum_square_dif/UUT
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).
#    Time: 2 ms  Iteration: 1  Instance: /tb_file_sum_square_dif/UUT

the problem is that my sum result has always an XXXXXX but in my actual code it gets result. (if i give the inputs manually).
can anyone tell me why?

The warnings seem to happen at the exact time when i am reading new input. But if i run it manually i get right results (and no X's of course) in any time.
 

Are you sure that the signal doesn't have multiple drivers (in the RTL) and the testbench.
Multiple drivers is what cause 'X'
 

No habla VHDL senor, but it looks like you may have forgotten to initialize some registers. In real hardware it will work because in real hardware these registers will just be "0" after configuration. In simulation if you don't provide an initial value you get precisely this sort of thing.
 
this kind of error will apear when you use some convert functions such as to_unsigned or cov_unsigned or conv_siged so for avoiding from these type of warnings as mrflibble said you have forgotten to initialize some registers in definition. Set signals to initial value your problem will be solved
 
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