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conversion of std_logic_vector to integer in port

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harerama

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HI.
For decoder program how to convert std_logic_vector to integer in PORT

library ieee;
use ieee.std_logic_1164.all;

entity dec is
port (sel: in std_logic_vector (2 downto 0);
res: out std_logic_vector (7 downto 0));
end dec;

architecture archi of dec is
begin
res <= "00000001" when sel = "000" else
"00000010" when sel = "001" else
"00000100" when sel = "010" else
"00001000" when sel = "011" else
"00010000" when sel = "100" else
"00100000" when sel = "101" else
"XXXXXXXX";
end archi;

Thanks in advance

Regards
Raghu
 

your code doesnt really have anything to do with converting a std_logic_vector to an integer. Do you just want an extra port?

but for general code:

use ieee.numeric_std.all;

output_int <= to_integer( unsigned( input_slv ) );
 
Below gcd program i want to change std_logic_vector to integer thats i plan to do.

Code: 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;


entity gcd is
  port (
    clk : in std_logic;
    reset : in std_logic;
    start : in std_logic;
    a : in std_logic_vector(15 downto 0);
    b : in std_logic_vector(15 downto 0);
    outp : out std_logic_vector(15 downto 0);
    done : out std_logic;
    ready : out std_logic
  );
end gcd;

architecture fsmd of gcd is


type state_type is (S_ENTRY, S_EXIT, S_001_001, S_001_002, S_001_003, S_001_004, S_002_001, S_003_001, S_004_001, S_004_002, S_004_003, S_005_001, S_005_002, S_005_003, S_006_001, S_006_002, S_007_001, S_007_002, S_008_001, S_008_002, S_008_003, S_009_001, S_009_002, S_009_003, S_010_001);
  signal current_state, next_state: state_type;
signal D_1966_1_reg : std_logic_vector(31 downto 0);
  signal D_1966_1_eval : std_logic_vector(31 downto 0);
  signal result_11_next : std_logic_vector(15 downto 0);
  signal result_11_reg : std_logic_vector(15 downto 0);
  signal result_11_eval : std_logic_vector(15 downto 0);
  signal x_1_next : std_logic_vector(15 downto 0);
  signal x_1_reg : std_logic_vector(15 downto 0);
  signal x_1_eval : std_logic_vector(15 downto 0);
  signal x_7_next : std_logic_vector(15 downto 0);
  signal x_7_reg : std_logic_vector(15 downto 0);
  signal x_7_eval : std_logic_vector(15 downto 0);
  signal y_7_next : std_logic_vector(15 downto 0);
  signal y_7_reg : std_logic_vector(15 downto 0);
  signal y_7_eval : std_logic_vector(15 downto 0);
  signal x_8_next : std_logic_vector(15 downto 0);
  signal x_8_reg : std_logic_vector(15 downto 0);
  signal x_8_eval : std_logic_vector(15 downto 0);
  signal y_8_next : std_logic_vector(15 downto 0);
  signal y_8_reg : std_logic_vector(15 downto 0);
  signal y_8_eval : std_logic_vector(15 downto 0);
  signal y_1_next : std_logic_vector(15 downto 0);
  signal y_1_reg : std_logic_vector(15 downto 0);
  signal y_1_eval : std_logic_vector(15 downto 0);
  signal result_9_next : std_logic_vector(15 downto 0);
  signal result_9_reg : std_logic_vector(15 downto 0);
  signal result_9_eval : std_logic_vector(15 downto 0);
  signal result_12_next : std_logic_vector(15 downto 0);
  signal result_12_reg : std_logic_vector(15 downto 0);
  signal result_12_eval : std_logic_vector(15 downto 0);
  signal D_1964_1_next : std_logic_vector(31 downto 0);
  signal D_1964_1_reg : std_logic_vector(31 downto 0);
  signal D_1964_1_eval : std_logic_vector(31 downto 0);
  signal D_1965_1_next : std_logic_vector(31 downto 0);
  signal D_1965_1_reg : std_logic_vector(31 downto 0);
  signal D_1965_1_eval : std_logic_vector(31 downto 0);
  signal x_5_next : std_logic_vector(15 downto 0);
  signal x_5_reg : std_logic_vector(15 downto 0);
  signal x_5_eval : std_logic_vector(15 downto 0);
  signal y_6_next : std_logic_vector(15 downto 0);
  signal y_6_reg : std_logic_vector(15 downto 0);
  signal y_6_eval : std_logic_vector(15 downto 0);
  signal outp_next : std_logic_vector(15 downto 0);
  signal outp_reg : std_logic_vector(15 downto 0);
  signal outp_eval : std_logic_vector(15 downto 0);
  constant CNST_0 : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
begin
process(clk.reset)
begin

begin (clk, reset)
     if (reset = '1') then
      current_state <= S_ENTRY;
      D_1966_1_reg <= (others => '0');
      result_11_reg <= (others => '0');
      x_1_reg <= (others => '0');
      x_7_reg <= (others => '0');
      y_7_reg <= (others => '0');
      x_8_reg <= (others => '0');
      y_8_reg <= (others => '0');
      y_1_reg <= (others => '0');
      result_9_reg <= (others => '0');
      result_12_reg <= (others => '0');
      D_1964_1_reg <= (others => '0');
      D_1965_1_reg <= (others => '0');
      x_5_reg <= (others => '0');
      y_6_reg <= (others => '0');
      outp_reg <= (others => '0');
    elsif (clk = '1' and clk'EVENT) then
      current_state <= next_state;
     -- D_1966_1_reg <= D_1966_1_next;
     D_1966_1_reg <= aa;
      result_11_reg <= result_11_next;
      x_1_reg <= x_1_next;
      x_7_reg <= x_7_next;
      y_7_reg <= y_7_next;
      x_8_reg <= x_8_next;
      y_8_reg <= y_8_next;
      y_1_reg <= y_1_next;
      result_9_reg <= result_9_next;
      result_12_reg <= result_12_next;
      D_1964_1_reg <= D_1964_1_next;
      D_1965_1_reg <= D_1965_1_next;
      x_5_reg <= x_5_next;
      y_6_reg <= y_6_next;
      outp_reg <= outp_next;
    end if;
  end process;

  -- next state and output logic
  process (current_state, start,
    a,
    b,
    outp_reg,
    D_1966_1_reg, D_1966_1_next,
    result_11_reg, result_11_next,
    x_1_reg, x_1_next,
    x_7_reg, x_7_next,
    y_7_reg, y_7_next,
    x_8_reg, x_8_next,
    y_8_reg, y_8_next,
    y_1_reg, y_1_next,
    result_9_reg, result_9_next,
    result_12_reg, result_12_next,
    D_1964_1_reg, D_1964_1_next,
    D_1965_1_reg, D_1965_1_next,
    x_5_reg, x_5_next,
    y_6_reg, y_6_next
  )
  begin
    done <= '0';
    ready <= '0';
    D_1966_1_next <= D_1966_1_reg;
    result_11_next <= result_11_reg;
    x_1_next <= x_1_reg;
    x_7_next <= x_7_reg;
    y_7_next <= y_7_reg;
    x_8_next <= x_8_reg;
    y_8_next <= y_8_reg;
    y_1_next <= y_1_reg;
    result_9_next <= result_9_reg;
    result_12_next <= result_12_reg;
    D_1964_1_next <= D_1964_1_reg;
    D_1965_1_next <= D_1965_1_reg;
    x_5_next <= x_5_reg;
    y_6_next <= y_6_reg;
    outp_next <= outp_reg;
    case current_state is
      when S_ENTRY =>
        ready <= '1';
        if (start = '1') then
          next_state <= S_001_001;
        else
          next_state <= S_ENTRY;
        end if;
      when S_001_001 =>
        x_1_next <= a(15 downto 0);
        y_1_next <= b(15 downto 0);
        next_state <= S_001_002;
      when S_001_002 =>
        x_8_next <= x_1_reg(15 downto 0);
        y_8_next <= y_1_reg(15 downto 0);
        if (x_1_reg /= CNST_0(15 downto 0)) then
          D_1964_1_next <= "00000000000000000000000000000001";
        else
          D_1964_1_next <= (others => '0');
        end if;
        if (y_1_reg /= CNST_0(15 downto 0)) then
          D_1965_1_next <= "00000000000000000000000000000001";
        else
          D_1965_1_next <= (others => '0');
        end if;
        next_state <= S_001_003;
      when S_001_003 =>
        D_1966_1_next <= D_1964_1_reg and D_1965_1_reg(31 downto 0);
        next_state <= S_001_004;
      when S_001_004 =>
        if (D_1966_1_reg /= CNST_0(15 downto 0)) then
          next_state <= S_002_001;
        else
          next_state <= S_009_001;
        end if;
      when S_002_001 =>
        next_state <= S_007_001;
      when S_003_001 =>
        if (x_8_reg >= y_8_reg(15 downto 0)) then
          next_state <= S_004_001;
        else
          next_state <= S_005_001;
        end if;
      when S_004_001 =>
        x_5_next <= std_logic_vector(unsigned(x_8_reg) - unsigned(y_8_reg(15 downto 0)));
        next_state <= S_004_002;
      when S_004_002 =>
        x_7_next <= x_5_reg(15 downto 0);
        next_state <= S_004_003;
      when S_004_003 =>
        next_state <= S_006_001;
      when S_005_001 =>
        y_6_next <= std_logic_vector(unsigned(y_8_reg) - unsigned(x_8_reg(15 downto 0)));
        next_state <= S_005_002;
      when S_005_002 =>
        y_7_next <= y_6_reg(15 downto 0);
        next_state <= S_005_003;
      when S_005_003 =>
        next_state <= S_006_001;
      when S_006_001 =>
        x_8_next <= x_7_reg(15 downto 0);
        y_8_next <= y_7_reg(15 downto 0);
        next_state <= S_006_002;
      when S_006_002 =>
        next_state <= S_007_001;
      when S_007_001 =>
        x_7_next <= x_8_reg(15 downto 0);
        y_7_next <= y_8_reg(15 downto 0);
        next_state <= S_007_002;
      when S_007_002 =>
        if (x_8_reg /= y_8_reg(15 downto 0)) then
          next_state <= S_003_001;
        else
          next_state <= S_008_001;
        end if;
      when S_008_001 =>
        result_9_next <= x_8_reg(15 downto 0);
        next_state <= S_008_002;
      when S_008_002 =>
        result_12_next <= result_9_reg(15 downto 0);
        next_state <= S_008_003;
      when S_008_003 =>
        next_state <= S_010_001;
      when S_009_001 =>
        result_11_next <= CNST_0(15 downto 0);
        next_state <= S_009_002;
      when S_009_002 =>
        result_12_next <= result_11_reg(15 downto 0);
        next_state <= S_009_003;
      when S_009_003 =>
        next_state <= S_010_001;
      when S_010_001 =>
        outp_next <= result_12_reg(15 downto 0);
        next_state <= S_EXIT;
      when S_EXIT =>
        done <= '1';
        next_state <= S_ENTRY;
      when others =>
        next_state <= S_ENTRY;
    end case;
  end process;

  outp <= outp_reg;

end fsmd;

Regards
Raghavendra
 
Last edited by a moderator:

You still dont say what you plan on converting to integer?
you want to replace all the std_logic_vectors with integers?
you want to do type conversion?
you want th ports to be integers?

what do you want?
 
actually i working on open source projects,as newbie.
conversion of std_logic_vector to integer work assigned me so i try to converting.
i want to convert both port and siganl in my code.
 

then all you need to do is replace std_logic_vector to integer.

---------- Post added at 13:50 ---------- Previous post was at 13:48 ----------

then all you need to do is replace std_logic_vector to integer.
For the 16 bit values, you will need to specify a range to prevent it using all 32 bits for the values.

And also remember that integers are signed. you'll have to work out which std_logic_vectors are meant to be signed and which are not and scale them accordingly
 

actually i done like this
signal D_1966_1_reg : integer;
signal temp: std_logic_vector(31 downto 0);
D_1966_1_reg <= conv_integer(temp);

after conversion ran an error : object class keyword such as 'variable' is expected

please guide me where i do converesion,

Thanks in advance
 

Why do you want to change to type "integer" ?
Why not change the ports and the signals to type "unsigned" ?

I think that is better if you are going to synthesize the circuit.

---------- Post added at 13:10 ---------- Previous post was at 13:05 ----------
harerama said:
signal D_1966_1_reg : integer;
signal temp: std_logic_vector(31 downto 0);
D_1966_1_reg <= conv_integer(temp);
Click to expand...

Don't use conv_integer. It is not part of numeric_std.
I recommend using "unsigned" instead, but if you really want integer:

D_1966_1_reg <= to_integer(unsigned(temp));

(or "signed" if temp has a sign bit)
 
You must have a "begin" between the signal/variable declarations and the statements.

Again, I think you should use "unsigned" for both ports and signals. No casts or conversions will be needed in the code.
 

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