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[SOLVED] help for over-current protector in LDO

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chaojixin

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Hi, every one!
I'm on the design of a 2.5~4.2V input, 1.8V output, 400mA LDO(CMOS process), and a over-current protection is needed.
What's the most used method in product?

the academic papers usually present a current mirror method as shown in the figure but I think the mismatch is high because the 'n' is always 1000 or even larger. does the product always use this method?
 

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Well, if the 2.5-4.2V is from the output of another regulator, do you really need an over current protection ? I don't think so....
 

chaojixin said:
... I think the mismatch is high because the 'n' is always 1000 or even larger.
Click to expand...
We used not a single Sensor MOS, but several of them, well distributed between the Power MOS fingers. The matching was quite adequate.
 

---------- Post added at 11:01 ---------- Previous post was at 10:37 ----------

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erikl said:
We used not a single Sensor MOS, but several of them, well distributed between the Power MOS fingers. The matching was quite adequate.
Click to expand...
thank you! But how much precision is adequate in general? I want do some calculation and simulation

---------- Post added at 11:01 ---------- Previous post was at 11:01 ----------
cks3976 said:
Well, if the 2.5-4.2V is from the output of another regulator, do you really need an over current protection ? I don't think so....
Click to expand...
it is from Li-on battery. in what condition an over current protection is not needed? I find that many datasheets of product present this feature
 
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chaojixin said:
... how much precision is adequate in general? I want do some calculation and simulation
Click to expand...
I think a ±10% precision is adequate for over-current protection. See the dataSheets of commercial LDOs.

As we used a trimming scheme for Vref anyway, we also had the chance to select and arbitrarily add the currents of several (distributed) sense current fingers, so eventually even came closer to the intended current limit.

Another hint: Use sense resistor(s) with positive TC and put it/them close to the power MOS .

For high current LDOs (>≈ 20..50mA) a bend-back I-V characteristic is preferable.
 
erikl said:
I think a ±10% precision is adequate for over-current protection. See the dataSheets of commercial LDOs.

As we used a trimming scheme for Vref anyway, we also had the chance to select and arbitrarily add the currents of several (distributed) sense current fingers, so eventually even came closer to the intended current limit.

Another hint: Use sense resistor(s) with positive TC and put it/them close to the power MOS .

For high current LDOs (>≈ 20..50mA) a bend-back I-V characteristic is preferable.
Click to expand...

I haven't heard about the 'bend-back I-V characteristic' method, can you please give a list of reference?
 

chaojixin said:
I haven't heard about the 'bend-back I-V characteristic' method, can you please give a list of reference?
Click to expand...
Guess I've used the wrong English designation, sorry! Search for "foldback current limiting" via G00gle images!
 
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