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You should first have ur hdl design synthesized, then optmiized using constraints, then do a PNR and finally generate a bit file using PROMGEN. After the bit file is generated depending upon ur FPGA, download it to the kit using the Xilinx JTAG/USB cable and the Xilinx iMPACT software. You can download it directly to FPGA or to the PROM on the board. Each has its advantages and disadvantages... refer to the Xilinx ISE manual for detailed steps.
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