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How to protect VHDL source code?

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Zerox100

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Hi,

I want to send one of my design to stranger that probably is a customer for testing (but i could not trust him at first). So i don't want to send the exact source code. is there any way to send compiled code to him at gate level or something like that?

Regards,
 

Re: VHDL Code Protection

If you are both using ModelSim, you can take a look at Chapter 3 of the user manual (here) to read about encrypted source.
**broken link removed**

There's another thread here for a similar topic:
https://www.edaboard.com/threads/220638/
 
Re: VHDL Code Protection

i am use 8 pin pic controller 2way self made connekt and CRC code
 

Re: VHDL Code Protection

No he doesn't want to simulate. I want to give him a partial solution and he should only synthesize design with other parts and program the FPGA. After that he probably ask me some changes and off course he will pay me. I want to give him a low level VHDL code that he couldn't change it himself. He should be able to verify the overall functionality of the design (Nothing else).

I bring an idea!!! Is it possible to give him the post synthesize model? Could he use a "post synthesize model" as a part of his project? The device is xilinx Spartan III.
 

Re: VHDL Code Protection

You can send the pre-compiled libraries, in which the VHDL files are compiled using -nodebug option of vcom. This hides all internal signals and hierarchy. You should refer to ModelSim user manual for more information.
 

Re: VHDL Code Protection

this or NGC files. NGC files are the synthesis output as a netlist -- before mapping/placement/routing. This works best when there are little or no extra timing/placement constraints for the core. At this point, the end user won't have the VHDL/Verilog. You would need to look up instruction on how to make an NGC of a specific portion of your design, making sure to handle IOB's correctly.

Popular IP cores often include code that will disable the core after some period of time has elapsed. for basic methods, it would still be possible to use FPGA editor to work around the protection without too much difficulty.
 
Re: VHDL Code Protection

serhannn said:
You can send the pre-compiled libraries, in which the VHDL files are compiled using -nodebug option of vcom. This hides all internal signals and hierarchy. You should refer to ModelSim user manual for more information.
Click to expand...

This only works if both parties are using the same version of ModelSim.
 

Re: VHDL Code Protection

Is it possible to use old program lenardo and compile to a standrad VHDL Library? For some reasons, It is better for me to use vhdl instead of netlist file.
 

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